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Searched refs:REG_FPGA0_XCD_RF_SW_CTRL (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8192f.c831 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_iqk_path_a()
988 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_a()
1055 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_iqk_path_b()
1153 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_b()
1217 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_b()
1283 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8192fu_phy_iqcalibrate()
1431 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400); in rtl8192fu_phy_iqcalibrate()
H A Drtl8xxxu_8192e.c1089 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8192eu_phy_iqcalibrate()
1121 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); in rtl8192eu_phy_iqcalibrate()
H A Drtl8xxxu_8723b.c933 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8723bu_phy_iqcalibrate()
965 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8723bu_phy_iqcalibrate()
H A Drtl8xxxu_8188f.c1086 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8188fu_phy_iqcalibrate()
1121 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); in rtl8188fu_phy_iqcalibrate()
H A Drtl8xxxu_8710b.c1294 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8710bu_phy_iqcalibrate()
1344 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); in rtl8710bu_phy_iqcalibrate()
H A Drtl8xxxu_8188e.c789 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8188eu_phy_iqcalibrate()
830 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8188eu_phy_iqcalibrate()
H A Drtl8xxxu_regs.h929 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 macro
H A Drtl8xxxu_core.c3217 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8xxxu_phy_iqcalibrate()
3256 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8xxxu_phy_iqcalibrate()