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Searched refs:REG_FLD_MOD (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5_core.c43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi5_core_ddc_init()
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi5_core_ddc_init()
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi5_core_ddc_init()
99 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); in hdmi5_core_ddc_init()
102 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); in hdmi5_core_ddc_init()
112 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); in hdmi5_core_ddc_uninit()
136 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, in hdmi5_core_ddc_read()
326 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, in hdmi_core_video_config()
347 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); in hdmi_core_config_video_packetizer()
351 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); in hdmi_core_config_video_packetizer()
[all …]
H A Dhdmi4_core.c40 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi4_core_ddc_init()
45 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi4_core_ddc_init()
55 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi4_core_ddc_init()
65 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); in hdmi4_core_ddc_init()
192 REG_FLD_MOD(core_sys_base, in hdmi_core_video_config()
216 REG_FLD_MOD(core_sys_base, in hdmi_core_video_config()
490 REG_FLD_MOD(av_base, in hdmi_core_audio_config()
492 REG_FLD_MOD(av_base, in hdmi_core_audio_config()
505 REG_FLD_MOD(av_base, HDMI_CORE_AV_FREQ_SVAL, in hdmi_core_audio_config()
816 REG_FLD_MOD(hdmi_av_base(core), in hdmi4_audio_start()
[all …]
H A Dhdmi4_cec.c108 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
116 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
128 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi_cec_clear_tx_fifo()
163 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3); in hdmi_cec_adap_enable()
166 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
203 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3); in hdmi_cec_adap_enable()
238 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
288 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4); in hdmi_cec_adap_transmit()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
H A Dhdmi_phy.c119 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes()
120 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
139 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure()
156 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure()
163 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure()
H A Ddss.c57 #define REG_FLD_MOD(dss, idx, val, start, end) \ macro
285 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable()
489 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
520 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap5()
549 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap4()
709 REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6); in dss_set_venc_output()
715 REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5); in dss_set_dac_pwrdn_bgz()
733 REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15); in dss_select_hdmi_venc_clk_source()
761 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17); in dss_dpi_select_source_omap4()
788 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16); in dss_dpi_select_source_omap5()
[all …]
H A Dhdmi_wp.c74 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
90 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
104 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); in hdmi_wp_video_start()
115 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); in hdmi_wp_video_stop()
135 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, in hdmi_wp_video_config_format()
266 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); in hdmi_wp_audio_enable()
273 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); in hdmi_wp_audio_core_req_enable()
H A Ddispc.c53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ macro
750 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
1952 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
2039 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2049 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2958 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
3259 REG_FLD_MOD(dispc, DISPC_CONTROL, in dispc_mgr_set_timings()
3788 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); in dispc_enable_sidle()
3947 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); in _omap_dispc_initial_config()
3955 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); in _omap_dispc_initial_config()
[all …]
H A Dhdmi5.c101 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
265 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi_start_audio_stream()
274 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); in hdmi_stop_audio_stream()
451 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi5_bridge_get_edid()
459 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); in hdmi5_bridge_get_edid()
H A Ddsi.c53 #define REG_FLD_MOD(dsi, idx, val, start, end) \ macro
848 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
886 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1232 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); in dsi_cio_power()
1614 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); in dsi_cio_init()
1619 REG_FLD_MOD(dsi, DSI_CLK_CTRL, in dsi_cio_init()
1641 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); in dsi_cio_uninit()
1856 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 0, 0); in dsi_vc_enable()
1911 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 9, 9); in dsi_vc_enable_hs()
3021 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 4, 4); in dsi_enable_video_mode()
[all …]
H A Dhdmi.h277 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
/openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5_core.c62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
148 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, in hdmi_core_ddc_edid()
326 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, in hdmi_core_video_config()
328 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, in hdmi_core_video_config()
332 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, in hdmi_core_video_config()
334 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, in hdmi_core_video_config()
345 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, in hdmi_core_video_config()
347 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, in hdmi_core_video_config()
351 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, in hdmi_core_video_config()
361 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, in hdmi_core_video_config()
[all …]
H A Dhdmi4_core.c41 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi_core_ddc_init()
46 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi_core_ddc_init()
56 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); in hdmi_core_ddc_init()
234 REG_FLD_MOD(core_sys_base, in hdmi_core_video_config()
258 REG_FLD_MOD(core_sys_base, in hdmi_core_video_config()
535 REG_FLD_MOD(av_base, in hdmi_core_audio_config()
537 REG_FLD_MOD(av_base, in hdmi_core_audio_config()
549 REG_FLD_MOD(av_base, in hdmi_core_audio_config()
860 REG_FLD_MOD(hdmi_av_base(core), in hdmi4_audio_start()
[all …]
H A Dhdmi_phy.c128 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes()
129 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
148 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure()
165 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure()
172 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure()
H A Ddss.c58 #define REG_FLD_MOD(idx, val, start, end) \ macro
285 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
289 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ in dss_sdi_enable()
301 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable()
445 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ in dss_select_dsi_clk_source()
480 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ in dss_select_lcd_clk_source()
616 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); in dss_set_venc_output()
675 REG_FLD_MOD(DSS_CONTROL, val, 17, 17); in dss_dpi_select_source_omap4()
701 REG_FLD_MOD(DSS_CONTROL, val, 17, 16); in dss_dpi_select_source_omap5()
1119 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); in dss_bind()
[all …]
H A Dhdmi_wp.c75 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
91 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
105 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); in hdmi_wp_video_start()
116 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); in hdmi_wp_video_stop()
136 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, in hdmi_wp_video_config_format()
246 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); in hdmi_wp_audio_enable()
253 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); in hdmi_wp_audio_core_req_enable()
H A Ddispc.c51 #define REG_FLD_MOD(idx, val, start, end) \ macro
276 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
773 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1043 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); in dispc_enable_gamma_table()
1665 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1757 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2840 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
2870 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); in dispc_mgr_enable_alpha_fixed_zorder()
2872 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); in dispc_mgr_enable_alpha_fixed_zorder()
3731 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); in _omap_dispc_initial_config()
[all …]
H A Dhdmi5.c97 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
318 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in read_edid()
322 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); in read_edid()
332 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi_start_audio_stream()
341 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); in hdmi_stop_audio_stream()
H A Ddsi.c113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ macro
1306 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
1349 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1986 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); in dsi_cio_enable_lane_override()
1995 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); in dsi_cio_disable_lane_override()
2154 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); in dsi_cio_init()
2160 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, in dsi_cio_init()
2188 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); in dsi_cio_uninit()
3130 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); in dsi_enter_ulps()
3170 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); in dsi_enter_ulps()
[all …]
H A Dhdmi.h258 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
/openbmc/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc.c445 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, in REG_FLD_MOD() function
2152 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k2g_plane_init()
2154 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k2g_plane_init()
2203 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); in dispc_k3_plane_init()
2204 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); in dispc_k3_plane_init()
2207 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k3_plane_init()
2209 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k3_plane_init()
2715 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); in dispc_softreset()