Searched refs:R9A07G043_CLK_P0_DIV2 (Results 1 – 3 of 3) sorted by relevance
19 LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,116 DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
29 #define R9A07G043_CLK_P0_DIV2 18 macro
420 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,423 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;