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Searched refs:PRIV_VERSION_1_10_0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu.c84 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
85 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
86 ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
123 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
124 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
125 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
438 env->priv_ver = PRIV_VERSION_1_10_0; in rv64_sifive_u_cpu_init()
456 env->priv_ver = PRIV_VERSION_1_10_0; in rv64_sifive_e_cpu_init()
574 env->priv_ver = PRIV_VERSION_1_10_0; in rv32_sifive_u_cpu_init()
592 env->priv_ver = PRIV_VERSION_1_10_0; in rv32_sifive_e_cpu_init()
[all …]
H A Dcpu.h81 PRIV_VERSION_1_10_0 = 0, enumerator
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c189 priv_version = PRIV_VERSION_1_10_0; in riscv_cpu_validate_priv_spec()