| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | idef-parser.y | 60 %token <rvalue> REG IMM PRED
237 | PRED
247 | IN PRED
321 | PRED '=' rvalue
478 | PRED
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| H A D | macros.inc | 91 #define fLSBNEWNOT(PRED) (fLSBNEW(~PRED))
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| H A D | README.rst | 203 | PRED
205 | IN PRED
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| /openbmc/qemu/target/hexagon/ |
| H A D | gen_tcg_hvx.h | 167 #define fGEN_TCG_VEC_CMOV(PRED) \ argument
172 tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \
576 #define fGEN_TCG_PRED_VEC_LOAD(GET_EA, PRED, DSTOFF, INC) \ argument
581 PRED; \
741 #define fGEN_TCG_PRED_VEC_STORE(GET_EA, PRED, SRCOFF, ALIGN, INC) \ argument
746 PRED; \
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| H A D | macros.h | 91 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \ argument
94 tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
557 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ argument
558 gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
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| H A D | gen_tcg.h | 327 #define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \ argument
332 PRED; \
384 #define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \ argument
389 PRED; \
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| /openbmc/qemu/target/hexagon/imported/mmvec/ |
| H A D | encode_ext.def | 69 #define LDST_BO(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_ai, 000,MID3,ttttt,i PRED iii,MIN3,VR…
70 #define LDST_PI(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_pi, 001,MID3,xxxxx,- PRED iii,MIN3,VR…
71 #define LDST_PM(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_ppu,011,MID3,xxxxx,u PRED ---,MIN3,VR…
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| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | usr.c | 577 FUNC, RESIN, SRC1, SRC2, PRED, RES, USR_RES) \ argument
582 uint8_t pred = PRED; \
589 #define TEST_XR_OP_RRp(FUNC, RESIN, SRC1, SRC2, PRED, RES, USR_RES) \ argument
591 FUNC, RESIN, SRC1, SRC2, PRED, RES, USR_RES)
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | macros.def | 1378 { PRED = (mem_store_conditional(thread,EA,SRC,SIZE,insn) ? 0xff : 0); },
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