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Searched refs:PPLL_REF_DIV (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.c214 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
253 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
256 OUTPLLP(PPLL_REF_DIV, in radeon_write_pll_regs()
261 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
268 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) in radeon_write_pll_regs()
270 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); in radeon_write_pll_regs()
277 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) in radeon_write_pll_regs()
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c623 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { in radeon_probe_pll_params()
647 m = (INPLL(PPLL_REF_DIV) & 0x3ff); in radeon_probe_pll_params()
689 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; in radeon_probe_pll_params()
768 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
1343 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1362 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1401 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
1404 OUTPLLP(PPLL_REF_DIV, in radeon_write_pll_regs()
1409 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
1416 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) in radeon_write_pll_regs()
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H A Daty128fb.c578 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); in aty_pll_readupdate()
603 aty_st_pll(PPLL_REF_DIV, in aty_pll_writeupdate()
604 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); in aty_pll_writeupdate()
969 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in aty128_timings()
978 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); in aty128_timings()
1336 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); in aty128_set_pll()
H A Dradeon_pm.c2449 tmp = INPLL(PPLL_REF_DIV);
2451 OUTPLL(PPLL_REF_DIV, tmp);
2452 INPLL(PPLL_REF_DIV);
/openbmc/linux/include/video/
H A Daty128.h244 #define PPLL_REF_DIV 0x0003 macro
H A Dradeon.h431 #define PPLL_REF_DIV 0x0003 macro
/openbmc/qemu/hw/display/
H A Dati_regs.h289 #define PPLL_REF_DIV 0x03 macro
/openbmc/u-boot/include/
H A Dradeon.h433 #define PPLL_REF_DIV 0x0003 macro