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Searched refs:PPLL_POST3_DIV_MASK (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/include/video/
H A Daty128.h270 #define PPLL_POST3_DIV_MASK 0x70000 macro
H A Dradeon.h995 #define PPLL_POST3_DIV_MASK 0x00070000 macro
/openbmc/qemu/hw/display/
H A Dati_regs.h315 #define PPLL_POST3_DIV_MASK 0x00070000 macro
/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.c216 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { in radeon_write_pll_regs()
265 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
/openbmc/u-boot/include/
H A Dradeon.h991 #define PPLL_POST3_DIV_MASK 0x00070000 macro
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c1364 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { in radeon_write_pll_regs()
1413 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
H A Daty128fb.c1342 div3 &= ~PPLL_POST3_DIV_MASK; in aty128_set_pll()