Searched refs:POSTDIV (Results 1 – 4 of 4) sorted by relevance
28 #define POSTDIV 0x128 macro
21 ; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|36 ; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|159 ; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
45 #define POSTDIV 0x128 macro485 parent_name, base + POSTDIV, fixed, flags); in davinci_pll_clk_register()960 DEBUG_REG(POSTDIV),
26 Describes the main PLL clock output (before POSTDIV). The node name must