| /openbmc/linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | bq24735.yaml | 40 The POR value is 0x0000h. This number is in mA (e.g. 8192).
48 The POR value is 0x0000h. This number is in mV (e.g. 19200).
56 The POR value is 0x1000h. This number is in mA (e.g. 8064).
|
| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 51 POR
52 - support critical POR setting changed via switch on board
168 CPLD POR setting registers
170 1. Set POR switch selection register (addr 0xFFB00011) to 0.
171 2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
176 After reset, the new POR setting will be implemented.
|
| H A D | README.P1010RDB-PB | 36 POR: support critical POR setting changed via switch on board
|
| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-snps-eusb2.c | 22 #define POR BIT(1) macro
271 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR); in qcom_snps_eusb2_hsphy_init()
331 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0); in qcom_snps_eusb2_hsphy_init()
|
| H A D | phy-qcom-snps-femto-v2.c | 31 #define POR BIT(1) macro
421 POR, POR); in qcom_snps_hsphy_init()
459 POR, 0); in qcom_snps_hsphy_init()
|
| /openbmc/u-boot/doc/device-tree-bindings/input/ |
| H A D | i8042.txt | 10 duplicate POR byte, which should be ignored.
|
| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | xlnx,zynqmp-gpio-modepin.yaml | 10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
|
| /openbmc/phosphor-state-manager/ |
| H A D | bmc_state_manager.cpp | 297 this->lastRebootCause(RebootCause::POR); in discoverLastRebootCause()
330 this->lastRebootCause(RebootCause::POR); in discoverLastRebootCause()
|
| /openbmc/qemu/target/mips/tcg/ |
| H A D | tx79.decode | 66 POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
|
| /openbmc/docs/designs/ |
| H A D | bmc-reboot-cause-update.md | 85 | POR | 0x00 | Do nothing |
94 In the original approach, **WDIOF_CARDRESET** was used to represent a **POR**
|
| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,usb-hs-28nm.yaml | 41 - description: POR reset
|
| /openbmc/linux/arch/arm/boot/dts/nxp/mxs/ |
| H A D | imx23-olinuxino.dts | 110 startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
|
| /openbmc/linux/drivers/soc/fsl/ |
| H A D | Kconfig | 16 enabling, power-onreset(POR) configuration monitoring, alternate
|
| /openbmc/qemu/hw/pci-host/ |
| H A D | sabre.c | 52 #define POR (1U << 31) macro
351 s->reset_control = POR; in sabre_reset()
|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/ |
| H A D | BMC.interface.yaml | 76 - name: "POR"
|
| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qdl-udoo.dtsi | 68 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
|
| /openbmc/qemu/include/hw/misc/ |
| H A D | xlnx-versal-crl.h | 210 FIELD(RST_FPD, POR, 0, 1)
|
| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mq-tqma8mq.dtsi | 276 /* Attention: wdog reset forcing POR needs baseboard support */
|
| H A D | imx8mn-tqma8mqnl.dtsi | 238 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
|
| H A D | imx8mm-tqma8mqml.dtsi | 254 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
|
| /openbmc/linux/Documentation/translations/sp_SP/process/ |
| H A D | kernel-docs.rst | 25 POR FAVOR, si conoce algún documento que no figura aquí, o si escribe un
|
| /openbmc/linux/Documentation/ABI/stable/ |
| H A D | sysfs-driver-firmware-zynqmp | 42 Register is reset only by a POR reset.
|
| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-pinephone-pro.dts | 119 * POR circuit.
|
| /openbmc/u-boot/board/ti/am335x/ |
| H A D | README | 83 Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
|
| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie.yaml | 269 - const: por # POR reset
|