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Searched refs:PM_LD_MISS_L1 (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/arch/powerpc/perf/
H A Dgeneric-compat-pmu.c65 EVENT(PM_LD_MISS_L1, 0x400f0)
107 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
122 GENERIC_EVENT_PTR(PM_LD_MISS_L1),
123 CACHE_EVENT_PTR(PM_LD_MISS_L1),
175 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
189 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
H A Dpower8-pmu.c108 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
130 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
161 GENERIC_EVENT_PTR(PM_LD_MISS_L1),
164 CACHE_EVENT_PTR(PM_LD_MISS_L1),
214 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
270 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
H A Dpower10-pmu.c126 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
156 GENERIC_EVENT_PTR(PM_LD_MISS_L1),
159 CACHE_EVENT_PTR(PM_LD_MISS_L1),
184 CACHE_EVENT_PTR(PM_LD_MISS_L1),
290 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
362 [C(RESULT_MISS)] = PM_LD_MISS_L1,
463 [C(RESULT_MISS)] = PM_LD_MISS_L1,
H A Dpower7-pmu.c327 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
383 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
399 GENERIC_EVENT_PTR(PM_LD_MISS_L1),
H A Dpower10-events-list.h25 EVENT(PM_LD_MISS_L1, 0x3e054);
H A Dpower8-events-list.h21 EVENT(PM_LD_MISS_L1, 0x3e054)
H A Dpower9-events-list.h22 EVENT(PM_LD_MISS_L1, 0x3e054)
H A Dpower9-pmu.c139 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
H A Dpower7-events-list.h248 EVENT(PM_LD_MISS_L1, 0x400f0)
/openbmc/linux/tools/testing/selftests/powerpc/pmu/event_code_tests/
H A Devent_alternatives_tests_p9.c13 #define PM_LD_MISS_L1 0x3e054 macro
84 event_init(&leader, PM_LD_MISS_L1); in event_alternatives_tests_p9()
H A Devent_alternatives_tests_p10.c13 #define PM_LD_MISS_L1 0x3e054 macro