Home
last modified time | relevance | path

Searched refs:PLL_WR_EN (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/include/video/
H A Daty128.h240 #define PLL_WR_EN 0x00000080 macro
H A Dmach64.h136 #define PLL_WR_EN 0x02 macro
H A Dradeon.h511 #define PLL_WR_EN 0x00000080 macro
/openbmc/qemu/hw/display/
H A Dati_regs.h285 #define PLL_WR_EN 0x00000080 macro
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_pm.c1483 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1518 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1639 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1657 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
2277 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2300 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2430 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2454 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
H A Dmach64_ct.c35 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); in aty_st_pll_ct()
38 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); in aty_st_pll_ct()
H A Daty128fb.c570 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); in _aty_st_pll()
H A Dradeon_base.c305 tmp = save & ~(0x3f | PLL_WR_EN); in radeon_pll_errata_after_data_slow()
/openbmc/u-boot/include/
H A Dradeon.h513 #define PLL_WR_EN 0x00000080 macro