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Searched refs:PLL_REFDIV_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dutmi-armada100.h24 #define PLL_REFDIV_MASK 0x0000000F macro
/openbmc/u-boot/drivers/usb/host/
H A Dutmi-armada100.c28 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); in utmi_phy_init()
/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-utmi.c36 #define PLL_REFDIV_MASK GENMASK(6, 0) macro
122 reg &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK | PLL_SEL_LPFR_MASK); in mvebu_cp110_utmi_port_setup()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h84 PLL_REFDIV_MASK = 0x3f, enumerator
H A Dcru_rk322x.h88 PLL_REFDIV_MASK = 0x3f, enumerator
H A Dcru_rk3128.h89 PLL_REFDIV_MASK = 0x3f, enumerator
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3036.c67 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
202 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
H A Dclk_rk322x.c65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
203 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
H A Dclk_rk3128.c62 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
270 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
H A Dclk_rk3328.c64 PLL_REFDIV_MASK = 0x3f, enumerator
267 PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
H A Dclk_rk3399.c79 PLL_REFDIV_MASK = 0x3f, enumerator
343 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, in rkclk_set_pll()
/openbmc/linux/drivers/clk/visconti/
H A Dpll.c42 #define PLL_REFDIV_MASK GENMASK(5, 0) macro
68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK; in visconti_pll_get_params()
/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c342 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()