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Searched refs:PLLE_SS_CNTL_SSCCENTER (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c936 #define PLLE_SS_CNTL_SSCCENTER (1 << 14) macro
1013 value &= ~PLLE_SS_CNTL_SSCCENTER; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1122 #define PLLE_SS_CNTL_SSCCENTER (1 << 14) macro
1227 value &= ~PLLE_SS_CNTL_SSCCENTER; in tegra_plle_enable()