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Searched refs:PLLE_SS_CNTL_SSCBYP (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c623 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
711 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
741 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c652 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
757 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
787 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c937 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
989 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
1026 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1123 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
1229 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()