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Searched refs:PLLE_SS_CNTL_INTERP_RESET (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c624 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
711 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
742 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c653 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
757 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
788 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c938 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
989 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
1033 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1124 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
1235 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c71 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) macro
75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
1673 val &= ~PLLE_SS_CNTL_INTERP_RESET; in clk_plle_tegra114_enable()
2516 val &= ~PLLE_SS_CNTL_INTERP_RESET; in clk_plle_tegra210_enable()