Searched refs:PLLE_SS_CNTL (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 932 #define PLLE_SS_CNTL 0x68 macro
988 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
991 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1011 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1023 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1025 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1032 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1034 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 620 #define PLLE_SS_CNTL 0x68 macro
710 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
713 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
734 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
747 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 649 #define PLLE_SS_CNTL 0x68 macro
756 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
759 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
780 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
793 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 1118 #define PLLE_SS_CNTL 0x68 macro
1219 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1230 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1236 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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