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Searched refs:PLL1 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg32 ; This section allows setting up the PLL1. Usually this will
57 ; This section can be used to configure the PLL1 and the EMIF3a registers
155 ; This section allows setting up the PLL1. Usually this will
165 ; This section can be used to configure the PLL1 and the EMIF3a registers
182 ; This section can be used to configure the PLL1 and the EMIF3a registers
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clks.h183 #define PLL1 176 macro
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt52 PLL children node for PLL1 to PLL4 : (see ref manual for details)
/openbmc/u-boot/drivers/video/tegra124/
H A Dsor.c562 DUMP_REG(PLL1); in dump_sor_reg()
721 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
H A Dsor.h251 #define PLL1 0x18 macro