| /openbmc/linux/sound/soc/codecs/ |
| H A D | ak4642.c | 115 #define PLL1 (1 << 5) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /openbmc/u-boot/board/Barix/ipam390/ |
| H A D | ipam390-ais-uart.cfg | 32 ; This section allows setting up the PLL1. Usually this will
57 ; This section can be used to configure the PLL1 and the EMIF3a registers
155 ; This section allows setting up the PLL1. Usually this will
165 ; This section can be used to configure the PLL1 and the EMIF3a registers
182 ; This section can be used to configure the PLL1 and the EMIF3a registers
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| /openbmc/linux/Documentation/arch/arm/sunxi/ |
| H A D | clocks.rst | 20 PLL1
31 PLL1 |
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 126 #define PLL1 117 macro
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| H A D | stm32mp13-clks.h | 19 #define PLL1 6 macro
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| H A D | stm32mp1-clks.h | 183 #define PLL1 176 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | stm32mp1-clks.h | 183 #define PLL1 176 macro
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| H A D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
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| /openbmc/linux/Documentation/devicetree/bindings/clock/st/ |
| H A D | st,flexgen.txt | 31 | | |PLL1 | | | | | | | | | |
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | zl10039.c | 40 PLL1, enumerator
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| /openbmc/u-boot/doc/ |
| H A D | README.Heterogeneous-SoCs | 54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
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| /openbmc/u-boot/drivers/video/tegra124/ |
| H A D | sor.c | 562 DUMP_REG(PLL1); in dump_sor_reg()
721 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
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| H A D | sor.h | 251 #define PLL1 0x18 macro
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | st,stm32mp1.txt | 52 PLL children node for PLL1 to PLL4 : (see ref manual for details)
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| /openbmc/linux/arch/mips/boot/dts/ingenic/ |
| H A D | gcw0.dts | 442 * Put high-speed peripherals under PLL1, such that we can change the
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| /openbmc/linux/drivers/clk/nxp/ |
| H A D | clk-lpc18xx-cgu.c | 519 LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-stm32mp1.c | 1773 PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
2093 PLL1,
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| H A D | Kconfig | 200 Y2 and Y3 derive from PLL1
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-dhcom-som.dtsi | 476 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
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