Searched refs:PLL0 (Results 1 – 16 of 16) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | microchip,mpfs-ccc.yaml | 24 - description: PLL0's control registers
35 - description: PLL0's refclk0
36 - description: PLL0's refclk1
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| H A D | starfive,jh7110-syscrg.yaml | 30 - description: PLL0
44 - description: PLL0
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| /openbmc/linux/sound/soc/codecs/ |
| H A D | ak4642.c | 116 #define PLL0 (1 << 4) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | zl10039.c | 39 PLL0 = 0, enumerator
218 ret = zl10039_write(state, PLL0, buf, sizeof(buf)); in zl10039_set_params()
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| /openbmc/u-boot/drivers/video/tegra124/ |
| H A D | sor.c | 493 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ in tegra_dc_sor_power_up()
513 tegra_sor_write_field(sor, PLL0, in tegra_dc_sor_power_up()
561 DUMP_REG(PLL0); in dump_sor_reg()
708 tegra_sor_writel(sor, PLL0, in tegra_dc_sor_enable_dp()
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| H A D | sor.h | 221 #define PLL0 0x17 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | qcom,gcc-msm8660.h | 256 #define PLL0 247 macro
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| H A D | qcom,gcc-msm8960.h | 284 #define PLL0 276 macro
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| H A D | qcom,gcc-mdm9615.h | 286 #define PLL0 276 macro
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| H A D | qcom,gcc-ipq806x.h | 229 #define PLL0 220 macro
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| H A D | pll.txt | 9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
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| /openbmc/linux/Documentation/devicetree/bindings/clock/st/ |
| H A D | st,flexgen.txt | 21 | | |PLL0 | | | | |Dividers| |Dividers| | |
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| /openbmc/linux/arch/mips/boot/dts/ingenic/ |
| H A D | gcw0.dts | 443 * PLL0 frequency on demand without having to suspend peripherals.
446 * Put the GPU under PLL0 since we want a higher frequency.
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| /openbmc/u-boot/board/Barix/ipam390/ |
| H A D | ipam390-ais-uart.cfg | 17 ; This section allows setting the PLL0 system clock with a
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | gcc-mdm9615.c | 1615 [PLL0] = &pll0.clkr,
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| H A D | gcc-ipq806x.c | 3067 [PLL0] = &pll0.clkr,
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