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Searched refs:PIPE_B (Results 1 – 25 of 37) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc_regs.h31 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
45 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
54 #define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
57 #define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
66 #define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
69 #define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
82 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
85 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
106 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
109 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
H A Dintel_display_device.c118 [PIPE_B] = CURSOR_B_OFFSET, \
124 [PIPE_B] = CURSOR_B_OFFSET, \
131 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
138 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
183 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
232 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
293 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
334 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
356 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
370 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
[all …]
H A Dskl_watermark.c850 .active_pipes = BIT(PIPE_B),
852 [PIPE_B] = BIT(DBUF_S1),
856 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
859 [PIPE_B] = BIT(DBUF_S2),
876 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
878 [PIPE_B] = BIT(DBUF_S1),
883 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
886 [PIPE_B] = BIT(DBUF_S1),
913 .active_pipes = BIT(PIPE_B),
915 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
[all …]
H A Dintel_display_limits.h18 PIPE_B, enumerator
35 TRANSCODER_B = PIPE_B,
H A Di9xx_wm.c278 case PIPE_B: in vlv_get_fifo_size()
721 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
722 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
728 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
771 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
772 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
783 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
784 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
796 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
797 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
[all …]
H A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
395 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
475 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
579 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
756 .irq_pipe_mask = BIT(PIPE_B),
923 .irq_pipe_mask = BIT(PIPE_B),
1079 .irq_pipe_mask = BIT(PIPE_B),
1175 .irq_pipe_mask = BIT(PIPE_B),
1352 .irq_pipe_mask = BIT(PIPE_B),
1510 .irq_pipe_mask = BIT(PIPE_B),
H A Dintel_dpio_phy.c678 case PIPE_B: in vlv_pipe_to_channel()
841 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
853 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
874 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
883 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
896 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
1006 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
H A Dintel_display_trace.h48 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
77 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
184 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
H A Dintel_fdi.c167 case PIPE_B: in ilk_check_fdi_lanes()
192 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
294 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
318 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
H A Dintel_display_power_well.c1047 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1048 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1054 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1062 intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
1356 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1488 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
H A Dintel_pipe_crc.c177 case PIPE_B: in vlv_pipe_crc_ctl_reg()
238 case PIPE_B: in vlv_undo_pipe_scramble_reset()
H A Dintel_pch_display.c51 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
70 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
H A Dintel_display_irq.c288 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
443 case PIPE_B: in i9xx_pipestat_irq_ack()
615 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
939 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
H A Dg4x_hdmi.c392 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
758 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
H A Dintel_pps.c40 case PIPE_B: in pps_name()
166 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
294 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1119 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
H A Dicl_dsi.c812 case PIPE_B: in gen11_dsi_configure_transcoder()
1215 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1559 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1701 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
H A Dintel_sprite.c398 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_sprite_update_arm()
1569 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1619 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
H A Di9xx_plane.c912 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1016 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
H A Dvlv_dsi.c968 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
993 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1831 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c122 MMIO_D(PIPEDSL(PIPE_B)); in iterate_generic_mmio()
130 MMIO_D(PIPESTAT(PIPE_B)); in iterate_generic_mmio()
134 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B)); in iterate_generic_mmio()
138 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B)); in iterate_generic_mmio()
142 MMIO_D(CURCNTR(PIPE_B)); in iterate_generic_mmio()
145 MMIO_D(CURPOS(PIPE_B)); in iterate_generic_mmio()
148 MMIO_D(CURBASE(PIPE_B)); in iterate_generic_mmio()
151 MMIO_D(CUR_FBC_CTL(PIPE_B)); in iterate_generic_mmio()
169 MMIO_D(DSPCNTR(PIPE_B)); in iterate_generic_mmio()
170 MMIO_D(DSPADDR(PIPE_B)); in iterate_generic_mmio()
[all …]
H A Di915_irq.c903 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
1084 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
1210 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c2277 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2278 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2286 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2287 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2310 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); in init_generic_mmio_info()
2313 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2316 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2469 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2471 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2473 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
[all …]
H A Dreg.h73 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
82 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
H A Ddisplay.c53 pipe = PIPE_B; in get_edp_pipe()
628 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
/openbmc/linux/drivers/video/fbdev/intelfb/
H A Dintelfbhw.h183 #define PIPE_B 1 macro

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