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Searched refs:PHY_CON2_RESET_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c144 val = PHY_CON2_RESET_VAL; in ddr3_mem_ctrl_init()
164 val = PHY_CON2_RESET_VAL; in ddr3_mem_ctrl_init()
697 val = PHY_CON2_RESET_VAL; in ddr3_mem_ctrl_init()
H A Dexynos5_setup.h265 #define PHY_CON2_RESET_VAL 0x00010004 macro