Searched refs:PHY_CON1_RESET_VAL (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-exynos/ | ||
| H A D | exynos5_setup.h | 259 #define PHY_CON1_RESET_VAL 0x09210100 macro |
| H A D | dmc_init_ddr3.c | 177 val = PHY_CON1_RESET_VAL; in ddr3_mem_ctrl_init() |