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Searched refs:PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dexynos7-clk.h136 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dexynos7420-clk.h139 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 macro
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos7.c951 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi686 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,