Searched refs:PHYCLK_USBDRD300_UDRD30_PHYCLK_USER (Results 1 – 4 of 4) sorted by relevance
137 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 macro
140 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 macro
955 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
685 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,