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Searched refs:PERF_SOFT_RST (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/
H A Dreset.c37 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
55 (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
65 writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
/openbmc/u-boot/board/mscc/ocelot/
H A Docelot.c30 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in mscc_switch_reset()
32 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, in mscc_switch_reset()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_devcpu_gcb.h9 #define PERF_SOFT_RST 0x90 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_devcpu_gcb.h13 #define PERF_SOFT_RST 0x8 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_devcpu_gcb.h9 #define PERF_SOFT_RST 0x8 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_devcpu_gcb.h11 #define PERF_SOFT_RST 0x8 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_devcpu_gcb.h11 #define PERF_SOFT_RST 0x8 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h470 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); in hal_vcoreiii_ddr_failed()