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Searched refs:PCC2_RBASE (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dpcc.c37 {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
38 {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
39 {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
40 {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
42 {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
43 {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
44 {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
45 {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
46 {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
47 {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h138 #define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) macro
180 #define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT))
203 #define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT))
204 #define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT))
208 #define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT))
209 #define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT))
212 #define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT))