1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 27bc1ca39SPeng Fan /* 37bc1ca39SPeng Fan * Copyright (C) 2016 Freescale Semiconductor, Inc. 47bc1ca39SPeng Fan */ 57bc1ca39SPeng Fan 67bc1ca39SPeng Fan #ifndef _MX7ULP_REGS_H_ 77bc1ca39SPeng Fan #define _MX7ULP_REGS_H_ 87bc1ca39SPeng Fan 97bc1ca39SPeng Fan #include <linux/sizes.h> 107bc1ca39SPeng Fan 117bc1ca39SPeng Fan #define CAAM_SEC_SRAM_BASE (0x26000000) 127bc1ca39SPeng Fan #define CAAM_SEC_SRAM_SIZE (SZ_32K) 137bc1ca39SPeng Fan #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) 147bc1ca39SPeng Fan 157bc1ca39SPeng Fan #define OCRAM_0_BASE (0x2F000000) 167bc1ca39SPeng Fan #define OCRAM_0_SIZE (SZ_128K) 177bc1ca39SPeng Fan #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) 187bc1ca39SPeng Fan 197bc1ca39SPeng Fan #define OCRAM_1_BASE (0x2F020000) 207bc1ca39SPeng Fan #define OCRAM_1_SIZE (SZ_128K) 217bc1ca39SPeng Fan #define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) 227bc1ca39SPeng Fan 237bc1ca39SPeng Fan #define TCML_BASE (0x1FFD0000) 247bc1ca39SPeng Fan #define TCMU_BASE (0x20000000) 257bc1ca39SPeng Fan 267bc1ca39SPeng Fan #define AIPS3_BASE (0x40800000UL) 277bc1ca39SPeng Fan #define AIPS3_SLOT_SIZE (SZ_64K) 287bc1ca39SPeng Fan #define AIPS2_BASE (0x40000000UL) 297bc1ca39SPeng Fan #define AIPS2_SLOT_SIZE (SZ_64K) 307bc1ca39SPeng Fan #define AIPS1_BASE (0x41080000UL) 317bc1ca39SPeng Fan #define AIPS1_SLOT_SIZE (SZ_4K) 327bc1ca39SPeng Fan #define AIPS0_BASE (0x41000000UL) 337bc1ca39SPeng Fan #define AIPS0_SLOT_SIZE (SZ_4K) 347bc1ca39SPeng Fan #define IOMUXC0_AIPS0_SLOT (61) 357bc1ca39SPeng Fan #define WDG0_AIPS0_SLOT (37) 367bc1ca39SPeng Fan #define WDG1_AIPS2_SLOT (61) 377bc1ca39SPeng Fan #define WDG2_AIPS2_SLOT (67) 387bc1ca39SPeng Fan #define WDG0_PCC0_SLOT (37) 397bc1ca39SPeng Fan #define IOMUXC1_AIPS3_SLOT (44) 407bc1ca39SPeng Fan #define CMC0_AIPS1_SLOT (36) 417bc1ca39SPeng Fan #define CMC1_AIPS2_SLOT (65) 427bc1ca39SPeng Fan #define SCG0_AIPS0_SLOT (39) 437bc1ca39SPeng Fan #define PCC0_AIPS0_SLOT (38) 447bc1ca39SPeng Fan #define PCC1_AIPS1_SLOT (50) 457bc1ca39SPeng Fan #define PCC2_AIPS2_SLOT (63) 467bc1ca39SPeng Fan #define PCC3_AIPS3_SLOT (51) 477bc1ca39SPeng Fan #define SCG1_AIPS2_SLOT (62) 487bc1ca39SPeng Fan #define SIM0_AIPS1_SLOT (35) 497bc1ca39SPeng Fan #define SIM1_AIPS1_SLOT (48) 507bc1ca39SPeng Fan #define USBOTG0_AIPS2_SLOT (51) 517bc1ca39SPeng Fan #define USBOTG1_AIPS2_SLOT (52) 527bc1ca39SPeng Fan #define USBPHY_AIPS2_SLOT (53) 537bc1ca39SPeng Fan #define USDHC0_AIPS2_SLOT (55) 547bc1ca39SPeng Fan #define USDHC1_AIPS2_SLOT (56) 557bc1ca39SPeng Fan #define RGPIO2P0_AIPS0_SLOT (15) 567bc1ca39SPeng Fan #define RGPIO2P1_AIPS2_SLOT (15) 577bc1ca39SPeng Fan #define IOMUXC0_AIPS0_SLOT (61) 587bc1ca39SPeng Fan #define OCOTP_CTRL_AIPS1_SLOT (38) 597bc1ca39SPeng Fan #define OCOTP_CTRL_PCC1_SLOT (38) 607bc1ca39SPeng Fan #define SIM1_PCC1_SLOT (48) 617bc1ca39SPeng Fan #define MMDC0_AIPS3_SLOT (43) 627bc1ca39SPeng Fan #define IOMUXC_DDR_AIPS3_SLOT (45) 637bc1ca39SPeng Fan 647bc1ca39SPeng Fan #define LPI2C0_AIPS0_SLOT (51) 657bc1ca39SPeng Fan #define LPI2C1_AIPS0_SLOT (52) 667bc1ca39SPeng Fan #define LPI2C2_AIPS0_SLOT (53) 677bc1ca39SPeng Fan #define LPI2C3_AIPS0_SLOT (54) 687bc1ca39SPeng Fan #define LPI2C4_AIPS2_SLOT (43) 697bc1ca39SPeng Fan #define LPI2C5_AIPS2_SLOT (44) 707bc1ca39SPeng Fan #define LPI2C6_AIPS3_SLOT (36) 717bc1ca39SPeng Fan #define LPI2C7_AIPS3_SLOT (37) 727bc1ca39SPeng Fan 737bc1ca39SPeng Fan #define LPUART0_PCC0_SLOT (58) 747bc1ca39SPeng Fan #define LPUART1_PCC0_SLOT (59) 757bc1ca39SPeng Fan #define LPUART2_PCC1_SLOT (43) 767bc1ca39SPeng Fan #define LPUART3_PCC1_SLOT (44) 777bc1ca39SPeng Fan #define LPUART0_AIPS0_SLOT (58) 787bc1ca39SPeng Fan #define LPUART1_AIPS0_SLOT (59) 797bc1ca39SPeng Fan #define LPUART2_AIPS1_SLOT (43) 807bc1ca39SPeng Fan #define LPUART3_AIPS1_SLOT (44) 817bc1ca39SPeng Fan #define LPUART4_AIPS2_SLOT (45) 827bc1ca39SPeng Fan #define LPUART5_AIPS2_SLOT (46) 837bc1ca39SPeng Fan #define LPUART6_AIPS3_SLOT (38) 847bc1ca39SPeng Fan #define LPUART7_AIPS3_SLOT (39) 857bc1ca39SPeng Fan 867bc1ca39SPeng Fan #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) 877bc1ca39SPeng Fan #define CORE_B_ROM_BASE (0x00000000) 887bc1ca39SPeng Fan 897bc1ca39SPeng Fan #define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE 907bc1ca39SPeng Fan #define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE 917bc1ca39SPeng Fan #define IRAM_BASE_ADDR OCRAM_0_BASE 927bc1ca39SPeng Fan #define IRAM_SIZE (SZ_128K + SZ_128K) 937bc1ca39SPeng Fan 947bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT0 (0<<8) 957bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT1 (1<<8) 967bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT2 (2<<8) 977bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT3 (3<<8) 987bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT4 (4<<8) 997bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT5 (5<<8) 1007bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT6 (6<<8) 1017bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT7 (7<<8) 1027bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT8 (8<<8) 1037bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT9 (9<<8) 1047bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT10 (10<<8) 1057bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT11 (11<<8) 1067bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT12 (12<<8) 1077bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT13 (13<<8) 1087bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT14 (14<<8) 1097bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT15 (15<<8) 1107bc1ca39SPeng Fan 1117bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT0 (0x0) 1127bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT1 (0x1) 1137bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT2 (0x2) 1147bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT3 (0x3) 1157bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT4 (0x4) 1167bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT5 (0x5) 1177bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT6 (0x6) 1187bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT7 (0x7) 1197bc1ca39SPeng Fan 1207bc1ca39SPeng Fan 1217bc1ca39SPeng Fan #define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) 1227bc1ca39SPeng Fan #define SIM_SOPT1_PMIC_STBY_REQ (1<<2) 1237bc1ca39SPeng Fan #define SIM_SOPT1_A7_SW_RESET (1<<0) 1247bc1ca39SPeng Fan 1257bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT_SHIFT (8) 1267bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT_MASK (0xF00) 1277bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) 1287bc1ca39SPeng Fan 1297bc1ca39SPeng Fan #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) 1307bc1ca39SPeng Fan #define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) 1317bc1ca39SPeng Fan #define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) 1327bc1ca39SPeng Fan #define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) 1337bc1ca39SPeng Fan #define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) 1347bc1ca39SPeng Fan #define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) 1357bc1ca39SPeng Fan #define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) 1367bc1ca39SPeng Fan #define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) 1377bc1ca39SPeng Fan #define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) 1387bc1ca39SPeng Fan #define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) 1397bc1ca39SPeng Fan #define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) 1407bc1ca39SPeng Fan #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) 1417bc1ca39SPeng Fan #define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ 1427bc1ca39SPeng Fan #define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) 1437bc1ca39SPeng Fan #define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) 1447bc1ca39SPeng Fan #define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) 1457bc1ca39SPeng Fan #define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) 1467bc1ca39SPeng Fan #define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) 1477bc1ca39SPeng Fan #define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) 1487bc1ca39SPeng Fan 1497bc1ca39SPeng Fan #define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) 1507bc1ca39SPeng Fan #define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) 1517bc1ca39SPeng Fan #define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) 1527bc1ca39SPeng Fan #define USB_PHY0_BASE_ADDR USBPHY_RBASE 1537bc1ca39SPeng Fan #define USB_BASE_ADDR USBOTG0_RBASE 1547bc1ca39SPeng Fan 1557bc1ca39SPeng Fan #define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) 1567bc1ca39SPeng Fan #define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) 1577bc1ca39SPeng Fan #define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) 1587bc1ca39SPeng Fan #define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) 1597bc1ca39SPeng Fan #define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) 1607bc1ca39SPeng Fan #define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) 1617bc1ca39SPeng Fan #define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) 1627bc1ca39SPeng Fan #define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) 1637bc1ca39SPeng Fan 1647bc1ca39SPeng Fan #define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) 1657bc1ca39SPeng Fan #define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) 1667bc1ca39SPeng Fan #define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) 1677bc1ca39SPeng Fan #define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) 1687bc1ca39SPeng Fan #define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) 1697bc1ca39SPeng Fan #define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) 1707bc1ca39SPeng Fan #define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) 1717bc1ca39SPeng Fan #define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) 1727bc1ca39SPeng Fan 1737bc1ca39SPeng Fan #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) 1747bc1ca39SPeng Fan #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) 1757bc1ca39SPeng Fan 1767bc1ca39SPeng Fan #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) 1777bc1ca39SPeng Fan #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) 1787bc1ca39SPeng Fan 1797bc1ca39SPeng Fan #define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) 1807bc1ca39SPeng Fan #define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) 1817bc1ca39SPeng Fan #define CMC0_SRS (CMC0_RBASE + 0x20) 1827bc1ca39SPeng Fan #define CMC0_SSRS (CMC0_RBASE + 0x28) 1837bc1ca39SPeng Fan #define CMC1_SRS (CMC1_RBASE + 0x20) 1847bc1ca39SPeng Fan #define CMC1_SSRS (CMC1_RBASE + 0x28) 1857bc1ca39SPeng Fan 1867bc1ca39SPeng Fan #define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) 1877bc1ca39SPeng Fan #define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) 1887bc1ca39SPeng Fan #define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) 1897bc1ca39SPeng Fan #define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) 1907bc1ca39SPeng Fan #define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) 1917bc1ca39SPeng Fan #define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) 1927bc1ca39SPeng Fan #define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) 1937bc1ca39SPeng Fan 1947bc1ca39SPeng Fan #define SCG_CSR (SCG0_RBASE + 0x010) 1957bc1ca39SPeng Fan #define SCG_RCCR (SCG0_RBASE + 0x014) 1967bc1ca39SPeng Fan #define SCG_VCCR (SCG0_RBASE + 0x018) 1977bc1ca39SPeng Fan #define SCG_HCCR (SCG0_RBASE + 0x01c) 1987bc1ca39SPeng Fan 1997bc1ca39SPeng Fan #define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) 2007bc1ca39SPeng Fan #define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) 2017bc1ca39SPeng Fan #define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) 2027bc1ca39SPeng Fan #define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) 2037bc1ca39SPeng Fan #define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) 2047bc1ca39SPeng Fan #define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) 2057bc1ca39SPeng Fan #define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) 2067bc1ca39SPeng Fan #define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) 2077bc1ca39SPeng Fan 2087bc1ca39SPeng Fan #define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) 2097bc1ca39SPeng Fan #define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) 2107bc1ca39SPeng Fan 2117bc1ca39SPeng Fan #define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) 2127bc1ca39SPeng Fan #define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) 2137bc1ca39SPeng Fan 2147bc1ca39SPeng Fan #define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) 2157bc1ca39SPeng Fan 2167bc1ca39SPeng Fan #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) 2177bc1ca39SPeng Fan #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) 2187bc1ca39SPeng Fan 2197bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) 2207bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) 2217bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) 2227bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) 2237bc1ca39SPeng Fan 2247bc1ca39SPeng Fan 2257bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) 2267bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) 2277bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) 2287bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) 2297bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) 2307bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) 2317bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) 2327bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) 2337bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) 2347bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) 2357bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) 2367bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) 2377bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) 2387bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) 2397bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) 2407bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) 2417bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) 2427bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) 2437bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) 2447bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) 2457bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) 2467bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) 2477bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) 2487bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) 2497bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) 2507bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) 2517bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) 2527bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) 2537bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) 2547bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) 2557bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) 2567bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) 2577bc1ca39SPeng Fan 2587bc1ca39SPeng Fan /* Remap the rgpio2p registers addr to driver's addr */ 2597bc1ca39SPeng Fan #define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE 2607bc1ca39SPeng Fan #define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) 2617bc1ca39SPeng Fan #define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) 2627bc1ca39SPeng Fan #define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) 2637bc1ca39SPeng Fan #define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) 2647bc1ca39SPeng Fan #define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) 2657bc1ca39SPeng Fan 2667bc1ca39SPeng Fan /* MMDC registers addresses */ 2677bc1ca39SPeng Fan #define MMDC_MDCTL_OFFSET (0x000) 2687bc1ca39SPeng Fan #define MMDC_MDPDC_OFFSET (0x004) 2697bc1ca39SPeng Fan #define MMDC_MDOTC_OFFSET (0x008) 2707bc1ca39SPeng Fan #define MMDC_MDCFG0_OFFSET (0x00C) 2717bc1ca39SPeng Fan #define MMDC_MDCFG1_OFFSET (0x010) 2727bc1ca39SPeng Fan #define MMDC_MDCFG2_OFFSET (0x014) 2737bc1ca39SPeng Fan #define MMDC_MDMISC_OFFSET (0x018) 2747bc1ca39SPeng Fan #define MMDC_MDSCR_OFFSET (0x01C) 2757bc1ca39SPeng Fan #define MMDC_MDREF_OFFSET (0x020) 2767bc1ca39SPeng Fan #define MMDC_MDRWD_OFFSET (0x02C) 2777bc1ca39SPeng Fan #define MMDC_MDOR_OFFSET (0x030) 2787bc1ca39SPeng Fan #define MMDC_MDMRR_OFFSET (0x034) 2797bc1ca39SPeng Fan #define MMDC_MDCFG3LP_OFFSET (0x038) 2807bc1ca39SPeng Fan #define MMDC_MDMR4_OFFSET (0x03C) 2817bc1ca39SPeng Fan #define MMDC_MDASP_OFFSET (0x040) 2827bc1ca39SPeng Fan 2837bc1ca39SPeng Fan #define MMDC_MAARCR_OFFSET (0x400) 2847bc1ca39SPeng Fan #define MMDC_MAPSR_OFFSET (0x404) 2857bc1ca39SPeng Fan #define MMDC_MAEXIDR0_OFFSET (0x408) 2867bc1ca39SPeng Fan #define MMDC_MAEXIDR1_OFFSET (0x40C) 2877bc1ca39SPeng Fan #define MMDC_MADPCR0_OFFSET (0x410) 2887bc1ca39SPeng Fan #define MMDC_MADPCR1_OFFSET (0x414) 2897bc1ca39SPeng Fan #define MMDC_MADPSR0_OFFSET (0x418) 2907bc1ca39SPeng Fan #define MMDC_MADPSR1_OFFSET (0x41C) 2917bc1ca39SPeng Fan #define MMDC_MADPSR2_OFFSET (0x420) 2927bc1ca39SPeng Fan #define MMDC_MADPSR3_OFFSET (0x424) 2937bc1ca39SPeng Fan #define MMDC_MADPSR4_OFFSET (0x428) 2947bc1ca39SPeng Fan #define MMDC_MADPSR5_OFFSET (0x42C) 2957bc1ca39SPeng Fan #define MMDC_MASBS0_OFFSET (0x430) 2967bc1ca39SPeng Fan #define MMDC_MASBS1_OFFSET (0x434) 2977bc1ca39SPeng Fan #define MMDC_MAGENP_OFFSET (0x440) 2987bc1ca39SPeng Fan 2997bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_OFFSET (0x800) 3007bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_OFFSET (0x804) 3017bc1ca39SPeng Fan #define MMDC_MPWLGCR_OFFSET (0x808) 3027bc1ca39SPeng Fan #define MMDC_MPWLDECTRL0_OFFSET (0x80C) 3037bc1ca39SPeng Fan #define MMDC_MPWLDECTRL1_OFFSET (0x810) 3047bc1ca39SPeng Fan #define MMDC_MPWLDLST_OFFSET (0x814) 3057bc1ca39SPeng Fan #define MMDC_MPODTCTRL_OFFSET (0x818) 3067bc1ca39SPeng Fan #define MMDC_MPREDQBY0DL_OFFSET (0x81C) 3077bc1ca39SPeng Fan #define MMDC_MPREDQBY1DL_OFFSET (0x820) 3087bc1ca39SPeng Fan #define MMDC_MPREDQBY2DL_OFFSET (0x824) 3097bc1ca39SPeng Fan #define MMDC_MPREDQBY3DL_OFFSET (0x828) 3107bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_OFFSET (0x82C) 3117bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_OFFSET (0x830) 3127bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_OFFSET (0x834) 3137bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_OFFSET (0x838) 3147bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_OFFSET (0x83C) 3157bc1ca39SPeng Fan #define MMDC_MPDGCTRL1_OFFSET (0x840) 3167bc1ca39SPeng Fan #define MMDC_MPDGDLST_OFFSET (0x844) 3177bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_OFFSET (0x848) 3187bc1ca39SPeng Fan #define MMDC_MPRDDLST_OFFSET (0x84C) 3197bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_OFFSET (0x850) 3207bc1ca39SPeng Fan #define MMDC_MPWRDLST_OFFSET (0x854) 3217bc1ca39SPeng Fan #define MMDC_MPSDCTRL_OFFSET (0x858) 3227bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_OFFSET (0x85C) 3237bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_OFFSET (0x860) 3247bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_OFFSET (0x864) 3257bc1ca39SPeng Fan #define MMDC_MPRDDLHWST0_OFFSET (0x868) 3267bc1ca39SPeng Fan #define MMDC_MPRDDLHWST1_OFFSET (0x86C) 3277bc1ca39SPeng Fan #define MMDC_MPWRDLHWST0_OFFSET (0x870) 3287bc1ca39SPeng Fan #define MMDC_MPWRDLHWST1_OFFSET (0x874) 3297bc1ca39SPeng Fan #define MMDC_MPWLHWERR_OFFSET (0x878) 3307bc1ca39SPeng Fan #define MMDC_MPDGHWST0_OFFSET (0x87C) 3317bc1ca39SPeng Fan #define MMDC_MPDGHWST1_OFFSET (0x880) 3327bc1ca39SPeng Fan #define MMDC_MPDGHWST2_OFFSET (0x884) 3337bc1ca39SPeng Fan #define MMDC_MPDGHWST3_OFFSET (0x888) 3347bc1ca39SPeng Fan #define MMDC_MPPDCMPR1_OFFSET (0x88C) 3357bc1ca39SPeng Fan #define MMDC_MPPDCMPR2_OFFSET (0x890) 3367bc1ca39SPeng Fan #define MMDC_MPSWDAR_OFFSET (0x894) 3377bc1ca39SPeng Fan #define MMDC_MPSWDRDR0_OFFSET (0x898) 3387bc1ca39SPeng Fan #define MMDC_MPSWDRDR1_OFFSET (0x89C) 3397bc1ca39SPeng Fan #define MMDC_MPSWDRDR2_OFFSET (0x8A0) 3407bc1ca39SPeng Fan #define MMDC_MPSWDRDR3_OFFSET (0x8A4) 3417bc1ca39SPeng Fan #define MMDC_MPSWDRDR4_OFFSET (0x8A8) 3427bc1ca39SPeng Fan #define MMDC_MPSWDRDR5_OFFSET (0x8AC) 3437bc1ca39SPeng Fan #define MMDC_MPSWDRDR6_OFFSET (0x8B0) 3447bc1ca39SPeng Fan #define MMDC_MPSWDRDR7_OFFSET (0x8B4) 3457bc1ca39SPeng Fan #define MMDC_MPMUR_OFFSET (0x8B8) 3467bc1ca39SPeng Fan #define MMDC_MPWRCADL_OFFSET (0x8BC) 3477bc1ca39SPeng Fan #define MMDC_MPDCCR_OFFSET (0x8C0) 3487bc1ca39SPeng Fan #define MMDC_MPBC_OFFSET (0x8C4) 3497bc1ca39SPeng Fan #define MMDC_MPSWDRAR_OFFSET (0x8C8) 3507bc1ca39SPeng Fan 3517bc1ca39SPeng Fan /* First MMDC invalid IPS address */ 3527bc1ca39SPeng Fan #define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) 3537bc1ca39SPeng Fan #define MMDC_REGS_BASE MMDC0_RBASE 3547bc1ca39SPeng Fan 3557bc1ca39SPeng Fan #define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) 3567bc1ca39SPeng Fan #define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) 3577bc1ca39SPeng Fan #define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) 3587bc1ca39SPeng Fan #define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) 3597bc1ca39SPeng Fan #define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) 3607bc1ca39SPeng Fan #define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) 3617bc1ca39SPeng Fan #define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) 3627bc1ca39SPeng Fan #define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) 3637bc1ca39SPeng Fan #define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) 3647bc1ca39SPeng Fan #define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) 3657bc1ca39SPeng Fan #define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) 3667bc1ca39SPeng Fan #define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) 3677bc1ca39SPeng Fan #define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) 3687bc1ca39SPeng Fan #define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) 3697bc1ca39SPeng Fan #define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) 3707bc1ca39SPeng Fan 3717bc1ca39SPeng Fan #define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) 3727bc1ca39SPeng Fan #define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) 3737bc1ca39SPeng Fan #define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) 3747bc1ca39SPeng Fan #define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) 3757bc1ca39SPeng Fan #define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) 3767bc1ca39SPeng Fan #define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) 3777bc1ca39SPeng Fan #define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) 3787bc1ca39SPeng Fan #define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) 3797bc1ca39SPeng Fan #define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) 3807bc1ca39SPeng Fan #define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) 3817bc1ca39SPeng Fan #define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) 3827bc1ca39SPeng Fan #define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) 3837bc1ca39SPeng Fan #define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) 3847bc1ca39SPeng Fan #define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) 3857bc1ca39SPeng Fan #define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) 3867bc1ca39SPeng Fan 3877bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) 3887bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) 3897bc1ca39SPeng Fan #define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) 3907bc1ca39SPeng Fan #define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) 3917bc1ca39SPeng Fan #define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) 3927bc1ca39SPeng Fan #define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) 3937bc1ca39SPeng Fan #define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) 3947bc1ca39SPeng Fan #define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) 3957bc1ca39SPeng Fan #define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) 3967bc1ca39SPeng Fan #define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) 3977bc1ca39SPeng Fan #define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) 3987bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) 3997bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) 4007bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) 4017bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) 4027bc1ca39SPeng Fan #define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) 4037bc1ca39SPeng Fan #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) 4047bc1ca39SPeng Fan #define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) 4057bc1ca39SPeng Fan #define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) 4067bc1ca39SPeng Fan #define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) 4077bc1ca39SPeng Fan #define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) 4087bc1ca39SPeng Fan #define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) 4097bc1ca39SPeng Fan #define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) 4107bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) 4117bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) 4127bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) 4137bc1ca39SPeng Fan #define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) 4147bc1ca39SPeng Fan #define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) 4157bc1ca39SPeng Fan #define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) 4167bc1ca39SPeng Fan #define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) 4177bc1ca39SPeng Fan #define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) 4187bc1ca39SPeng Fan #define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) 4197bc1ca39SPeng Fan #define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) 4207bc1ca39SPeng Fan #define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) 4217bc1ca39SPeng Fan #define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) 4227bc1ca39SPeng Fan #define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) 4237bc1ca39SPeng Fan #define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) 4247bc1ca39SPeng Fan #define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) 4257bc1ca39SPeng Fan #define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) 4267bc1ca39SPeng Fan #define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) 4277bc1ca39SPeng Fan #define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) 4287bc1ca39SPeng Fan #define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) 4297bc1ca39SPeng Fan #define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) 4307bc1ca39SPeng Fan #define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) 4317bc1ca39SPeng Fan #define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) 4327bc1ca39SPeng Fan #define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) 4337bc1ca39SPeng Fan #define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) 4347bc1ca39SPeng Fan #define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) 4357bc1ca39SPeng Fan #define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) 4367bc1ca39SPeng Fan #define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) 4377bc1ca39SPeng Fan #define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) 4387bc1ca39SPeng Fan 4397bc1ca39SPeng Fan /* MMDC registers bit defines */ 4407bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_0 (31) 4417bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_1 (30) 4427bc1ca39SPeng Fan #define MMDC_MDCTL_ROW (24) 4437bc1ca39SPeng Fan #define MMDC_MDCTL_COL (20) 4447bc1ca39SPeng Fan #define MMDC_MDCTL_BL (19) 4457bc1ca39SPeng Fan #define MMDC_MDCTL_DSIZ (16) 4467bc1ca39SPeng Fan 4477bc1ca39SPeng Fan /* MDMISC */ 4487bc1ca39SPeng Fan #define MMDC_MDMISC_CS0_RDY (31) 4497bc1ca39SPeng Fan #define MMDC_MDMISC_CS1_RDY (30) 4507bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_DEL (22) 4517bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_GATING (21) 4527bc1ca39SPeng Fan #define MMDC_MDMISC_CALIB_PER_CS (20) 4537bc1ca39SPeng Fan #define MMDC_MDMISC_ADDR_MIRROR (19) 4547bc1ca39SPeng Fan #define MMDC_MDMISC_LHD (18) 4557bc1ca39SPeng Fan #define MMDC_MDMISC_WALAT (16) 4567bc1ca39SPeng Fan #define MMDC_MDMISC_BI (12) 4577bc1ca39SPeng Fan #define MMDC_MDMISC_LPDDR2_S (11) 4587bc1ca39SPeng Fan #define MMDC_MDMISC_MIF3_MODE (9) 4597bc1ca39SPeng Fan #define MMDC_MDMISC_RALAT (6) 4607bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_4_BANK (5) 4617bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_TYPE (3) 4627bc1ca39SPeng Fan #define MMDC_MDMISC_RST (1) 4637bc1ca39SPeng Fan 4647bc1ca39SPeng Fan /* MPWLGCR */ 4657bc1ca39SPeng Fan #define MMDC_MPWLGCR_WL_HW_ERR (8) 4667bc1ca39SPeng Fan 4677bc1ca39SPeng Fan /* MDSCR */ 4687bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_MSB (24) 4697bc1ca39SPeng Fan #define MMDC_MDSCR_MR_OP (24) 4707bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_LSB (16) 4717bc1ca39SPeng Fan #define MMDC_MDSCR_MR_ADDR (16) 4727bc1ca39SPeng Fan #define MMDC_MDSCR_CON_REQ (15) 4737bc1ca39SPeng Fan #define MMDC_MDSCR_CON_ACK (14) 4747bc1ca39SPeng Fan #define MMDC_MDSCR_MRR_READ_DATA_VALID (10) 4757bc1ca39SPeng Fan #define MMDC_MDSCR_WL_EN (9) 4767bc1ca39SPeng Fan #define MMDC_MDSCR_CMD (4) 4777bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_CS (3) 4787bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_BA (0) 4797bc1ca39SPeng Fan 4807bc1ca39SPeng Fan /* MPZQHWCTRL */ 4817bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) 4827bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_MODE (0) 4837bc1ca39SPeng Fan 4847bc1ca39SPeng Fan /* MPZQSWCTRL */ 4857bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) 4867bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) 4877bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) 4887bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) 4897bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) 4907bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) 4917bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) 4927bc1ca39SPeng Fan 4937bc1ca39SPeng Fan /* MPDGCTRL0 */ 4947bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_RST_RD_FIFO (31) 4957bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_CMP_CYC (30) 4967bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_DIS (29) 4977bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_EN (28) 4987bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_ERR (12) 4997bc1ca39SPeng Fan 5007bc1ca39SPeng Fan /* MPRDDLHWCTL */ 5017bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) 5027bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) 5037bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) 5047bc1ca39SPeng Fan 5057bc1ca39SPeng Fan /* MPWRDLHWCTL */ 5067bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) 5077bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) 5087bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) 5097bc1ca39SPeng Fan 5107bc1ca39SPeng Fan /* MPSWDAR */ 5117bc1ca39SPeng Fan #define MMDC_MPSWDAR_TEST_DUMMY_EN (6) 5127bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP3 (5) 5137bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP2 (4) 5147bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP1 (3) 5157bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP0 (2) 5167bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_RD (1) 5177bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_WR (0) 5187bc1ca39SPeng Fan 5197bc1ca39SPeng Fan /* MADPCR0 */ 5207bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS (9) 5217bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS_EN (8) 5227bc1ca39SPeng Fan 5237bc1ca39SPeng Fan /* MASBS1 */ 5247bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_VLD (0) 5257bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_TYPE (1) 5267bc1ca39SPeng Fan 5277bc1ca39SPeng Fan /* MDREF */ 5287bc1ca39SPeng Fan #define MMDC_MDREF_REF_CNT (16) 5297bc1ca39SPeng Fan #define MMDC_MDREF_REF_SEL (14) 5307bc1ca39SPeng Fan #define MMDC_MDREF_REFR (11) 5317bc1ca39SPeng Fan #define MMDC_MDREF_START_REF (0) 5327bc1ca39SPeng Fan 5337bc1ca39SPeng Fan /* MPWLGCR */ 5347bc1ca39SPeng Fan #define MMDC_MPWLGCR_HW_WL_EN (0) 5357bc1ca39SPeng Fan 5367bc1ca39SPeng Fan /* MPBC */ 5377bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DM_LP_EN (0) 5387bc1ca39SPeng Fan #define MMDC_MPBC_BIST_CA0_LP_EN (1) 5397bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ0_LP_EN (3) 5407bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ1_LP_EN (4) 5417bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ2_LP_EN (5) 5427bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ3_LP_EN (6) 5437bc1ca39SPeng Fan 5447bc1ca39SPeng Fan /* MPMUR */ 5457bc1ca39SPeng Fan #define MMDC_MPMUR_FRC_MSR (11) 5467bc1ca39SPeng Fan 5477bc1ca39SPeng Fan /* MPODTCTRL */ 5487bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) 5497bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) 5507bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) 5517bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) 5527bc1ca39SPeng Fan 5537bc1ca39SPeng Fan /* MAPSR */ 5547bc1ca39SPeng Fan #define MMDC_MAPSR_DVACK (25) 5557bc1ca39SPeng Fan #define MMDC_MAPSR_LPACK (24) 5567bc1ca39SPeng Fan #define MMDC_MAPSR_DVFS (21) 5577bc1ca39SPeng Fan #define MMDC_MAPSR_LPMD (20) 5587bc1ca39SPeng Fan 5597bc1ca39SPeng Fan /* MAARCR */ 5607bc1ca39SPeng Fan #define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) 5617bc1ca39SPeng Fan 5627bc1ca39SPeng Fan /* MPZQLP2CTL */ 5637bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) 5647bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) 5657bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) 5667bc1ca39SPeng Fan 5677bc1ca39SPeng Fan /* MDCFG3LP */ 5687bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRC_LP (16) 5697bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRCD_LP (8) 5707bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPpb_LP (4) 5717bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPab_LP (0) 5727bc1ca39SPeng Fan 5737bc1ca39SPeng Fan /* MDOR */ 5747bc1ca39SPeng Fan #define MMDC_MDOR_tXPR (16) 5757bc1ca39SPeng Fan #define MMDC_MDOR_SDE_to_RST (8) 5767bc1ca39SPeng Fan #define MMDC_MDOR_RST_to_CKE (0) 5777bc1ca39SPeng Fan 5787bc1ca39SPeng Fan /* MDCFG0 */ 5797bc1ca39SPeng Fan #define MMDC_MDCFG0_tRFC (24) 5807bc1ca39SPeng Fan #define MMDC_MDCFG0_tXS (16) 5817bc1ca39SPeng Fan #define MMDC_MDCFG0_tXP (13) 5827bc1ca39SPeng Fan #define MMDC_MDCFG0_tXPDLL (9) 5837bc1ca39SPeng Fan #define MMDC_MDCFG0_tFAW (4) 5847bc1ca39SPeng Fan #define MMDC_MDCFG0_tCL (0) 5857bc1ca39SPeng Fan 5867bc1ca39SPeng Fan /* MDCFG1 */ 5877bc1ca39SPeng Fan #define MMDC_MDCFG1_tRCD (29) 5887bc1ca39SPeng Fan #define MMDC_MDCFG1_tRP (26) 5897bc1ca39SPeng Fan #define MMDC_MDCFG1_tRC (21) 5907bc1ca39SPeng Fan #define MMDC_MDCFG1_tRAS (16) 5917bc1ca39SPeng Fan #define MMDC_MDCFG1_tRPA (15) 5927bc1ca39SPeng Fan #define MMDC_MDCFG1_tWR (9) 5937bc1ca39SPeng Fan #define MMDC_MDCFG1_tMRD (5) 5947bc1ca39SPeng Fan #define MMDC_MDCFG1_tCWL (0) 5957bc1ca39SPeng Fan 5967bc1ca39SPeng Fan /* MDCFG2 */ 5977bc1ca39SPeng Fan #define MMDC_MDCFG2_tDLLK (16) 5987bc1ca39SPeng Fan #define MMDC_MDCFG2_tRTP (6) 5997bc1ca39SPeng Fan #define MMDC_MDCFG2_tWTR (3) 6007bc1ca39SPeng Fan #define MMDC_MDCFG2_tRRD (0) 6017bc1ca39SPeng Fan 6027bc1ca39SPeng Fan /* MDRWD */ 6037bc1ca39SPeng Fan #define MMDC_MDRWD_tDAI (16) 6047bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_SAME (12) 6057bc1ca39SPeng Fan #define MMDC_MDRWD_WTR_DIFF (9) 6067bc1ca39SPeng Fan #define MMDC_MDRWD_WTW_DIFF (6) 6077bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_DIFF (3) 6087bc1ca39SPeng Fan #define MMDC_MDRWD_RTR_DIFF (0) 6097bc1ca39SPeng Fan 6107bc1ca39SPeng Fan /* MDPDC */ 6117bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_1 (28) 6127bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_0 (24) 6137bc1ca39SPeng Fan #define MMDC_MDPDC_tCKE (16) 6147bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_1 (12) 6157bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_0 (8) 6167bc1ca39SPeng Fan #define MMDC_MDPDC_SLOW_PD (7) 6177bc1ca39SPeng Fan #define MMDC_MDPDC_BOTH_CS_PD (6) 6187bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRX (3) 6197bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRE (0) 6207bc1ca39SPeng Fan 6217bc1ca39SPeng Fan /* MDASP */ 6227bc1ca39SPeng Fan #define MMDC_MDASP_CS0_END (0) 6237bc1ca39SPeng Fan 6247bc1ca39SPeng Fan /* MAEXIDR0 */ 6257bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) 6267bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) 6277bc1ca39SPeng Fan 6287bc1ca39SPeng Fan /* MAEXIDR1 */ 6297bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) 6307bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) 6317bc1ca39SPeng Fan 6327bc1ca39SPeng Fan /* MPWRDLCTL */ 6337bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) 6347bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) 6357bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) 6367bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) 6377bc1ca39SPeng Fan 6387bc1ca39SPeng Fan /* MPRDDLCTL */ 6397bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) 6407bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) 6417bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) 6427bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) 6437bc1ca39SPeng Fan 6447bc1ca39SPeng Fan /* MPWRDQBY0DL */ 6457bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) 6467bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) 6477bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) 6487bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) 6497bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) 6507bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) 6517bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) 6527bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) 6537bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) 6547bc1ca39SPeng Fan 6557bc1ca39SPeng Fan /* MPWRDQBY1DL */ 6567bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) 6577bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) 6587bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) 6597bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) 6607bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) 6617bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) 6627bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) 6637bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) 6647bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) 6657bc1ca39SPeng Fan 6667bc1ca39SPeng Fan /* MPWRDQBY2DL */ 6677bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) 6687bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) 6697bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) 6707bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) 6717bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) 6727bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) 6737bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) 6747bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) 6757bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) 6767bc1ca39SPeng Fan 6777bc1ca39SPeng Fan /* MPWRDQBY3DL */ 6787bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) 6797bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) 6807bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) 6817bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) 6827bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) 6837bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) 6847bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) 6857bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) 6867bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) 6877bc1ca39SPeng Fan 6887bc1ca39SPeng Fan /* Fields masks */ 6897bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) 6907bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) 6917bc1ca39SPeng Fan #define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) 6927bc1ca39SPeng Fan #define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) 6937bc1ca39SPeng Fan #define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) 6947bc1ca39SPeng Fan #define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) 6957bc1ca39SPeng Fan 6967bc1ca39SPeng Fan /* MDMISC */ 6977bc1ca39SPeng Fan #define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) 6987bc1ca39SPeng Fan #define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) 6997bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) 7007bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) 7017bc1ca39SPeng Fan #define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) 7027bc1ca39SPeng Fan #define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) 7037bc1ca39SPeng Fan #define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) 7047bc1ca39SPeng Fan #define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) 7057bc1ca39SPeng Fan #define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) 7067bc1ca39SPeng Fan #define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) 7077bc1ca39SPeng Fan #define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) 7087bc1ca39SPeng Fan #define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) 7097bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) 7107bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) 7117bc1ca39SPeng Fan #define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) 7127bc1ca39SPeng Fan 7137bc1ca39SPeng Fan /* MPWLGCR */ 7147bc1ca39SPeng Fan #define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) 7157bc1ca39SPeng Fan 7167bc1ca39SPeng Fan /* MDSCR */ 7177bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) 7187bc1ca39SPeng Fan #define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) 7197bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) 7207bc1ca39SPeng Fan #define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) 7217bc1ca39SPeng Fan #define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) 7227bc1ca39SPeng Fan #define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) 7237bc1ca39SPeng Fan #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) 7247bc1ca39SPeng Fan #define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) 7257bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) 7267bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) 7277bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) 7287bc1ca39SPeng Fan 7297bc1ca39SPeng Fan /* MPZQHWCTRL */ 7307bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) 7317bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) 7327bc1ca39SPeng Fan 7337bc1ca39SPeng Fan /* MPZQSWCTRL */ 7347bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) 7357bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) 7367bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) 7377bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) 7387bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) 7397bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) 7407bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) 7417bc1ca39SPeng Fan 7427bc1ca39SPeng Fan /* MPDGCTRL0 */ 7437bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) 7447bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) 7457bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) 7467bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) 7477bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) 7487bc1ca39SPeng Fan 7497bc1ca39SPeng Fan /* MPRDDLHWCTL */ 7507bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) 7517bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) 7527bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) 7537bc1ca39SPeng Fan 7547bc1ca39SPeng Fan /* MPWRDLHWCTL */ 7557bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) 7567bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) 7577bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) 7587bc1ca39SPeng Fan 7597bc1ca39SPeng Fan /* MPSWDAR */ 7607bc1ca39SPeng Fan #define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) 7617bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) 7627bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) 7637bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) 7647bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) 7657bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) 7667bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) 7677bc1ca39SPeng Fan 7687bc1ca39SPeng Fan /* MADPCR0 */ 7697bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) 7707bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) 7717bc1ca39SPeng Fan 7727bc1ca39SPeng Fan /* MASBS1 */ 7737bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) 7747bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) 7757bc1ca39SPeng Fan 7767bc1ca39SPeng Fan /* MDREF */ 7777bc1ca39SPeng Fan #define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) 7787bc1ca39SPeng Fan #define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) 7797bc1ca39SPeng Fan #define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) 7807bc1ca39SPeng Fan #define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) 7817bc1ca39SPeng Fan 7827bc1ca39SPeng Fan /* MPWLGCR */ 7837bc1ca39SPeng Fan #define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) 7847bc1ca39SPeng Fan 7857bc1ca39SPeng Fan /* MPBC */ 7867bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) 7877bc1ca39SPeng Fan #define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) 7887bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) 7897bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) 7907bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) 7917bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) 7927bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) 7937bc1ca39SPeng Fan 7947bc1ca39SPeng Fan /* MPMUR */ 7957bc1ca39SPeng Fan #define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) 7967bc1ca39SPeng Fan 7977bc1ca39SPeng Fan /* MPODTCTRL */ 7987bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) 7997bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) 8007bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) 8017bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) 8027bc1ca39SPeng Fan 8037bc1ca39SPeng Fan /* MAPSR */ 8047bc1ca39SPeng Fan #define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) 8057bc1ca39SPeng Fan #define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) 8067bc1ca39SPeng Fan #define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) 8077bc1ca39SPeng Fan #define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) 8087bc1ca39SPeng Fan 8097bc1ca39SPeng Fan /* MAARCR */ 8107bc1ca39SPeng Fan #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) 8117bc1ca39SPeng Fan 8127bc1ca39SPeng Fan /* MPZQLP2CTL */ 8137bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) 8147bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) 8157bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) 8167bc1ca39SPeng Fan 8177bc1ca39SPeng Fan /* MDCFG3LP */ 8187bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) 8197bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) 8207bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) 8217bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) 8227bc1ca39SPeng Fan 8237bc1ca39SPeng Fan /* MDOR */ 8247bc1ca39SPeng Fan #define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) 8257bc1ca39SPeng Fan #define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) 8267bc1ca39SPeng Fan #define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) 8277bc1ca39SPeng Fan 8287bc1ca39SPeng Fan /* MDCFG0 */ 8297bc1ca39SPeng Fan #define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) 8307bc1ca39SPeng Fan #define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) 8317bc1ca39SPeng Fan #define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) 8327bc1ca39SPeng Fan #define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) 8337bc1ca39SPeng Fan #define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) 8347bc1ca39SPeng Fan #define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) 8357bc1ca39SPeng Fan 8367bc1ca39SPeng Fan /* MDCFG1 */ 8377bc1ca39SPeng Fan #define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) 8387bc1ca39SPeng Fan #define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) 8397bc1ca39SPeng Fan #define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) 8407bc1ca39SPeng Fan #define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) 8417bc1ca39SPeng Fan #define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) 8427bc1ca39SPeng Fan #define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) 8437bc1ca39SPeng Fan #define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) 8447bc1ca39SPeng Fan #define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) 8457bc1ca39SPeng Fan 8467bc1ca39SPeng Fan /* MDCFG2 */ 8477bc1ca39SPeng Fan #define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) 8487bc1ca39SPeng Fan #define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) 8497bc1ca39SPeng Fan #define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) 8507bc1ca39SPeng Fan #define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) 8517bc1ca39SPeng Fan 8527bc1ca39SPeng Fan /* MDRWD */ 8537bc1ca39SPeng Fan #define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) 8547bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) 8557bc1ca39SPeng Fan #define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) 8567bc1ca39SPeng Fan #define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) 8577bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) 8587bc1ca39SPeng Fan #define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) 8597bc1ca39SPeng Fan 8607bc1ca39SPeng Fan /* MDPDC */ 8617bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) 8627bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) 8637bc1ca39SPeng Fan #define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) 8647bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) 8657bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) 8667bc1ca39SPeng Fan #define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) 8677bc1ca39SPeng Fan #define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) 8687bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) 8697bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) 8707bc1ca39SPeng Fan 8717bc1ca39SPeng Fan /* MDASP */ 8727bc1ca39SPeng Fan #define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) 8737bc1ca39SPeng Fan 8747bc1ca39SPeng Fan /* MAEXIDR0 */ 8757bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) 8767bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) 8777bc1ca39SPeng Fan 8787bc1ca39SPeng Fan /* MAEXIDR1 */ 8797bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) 8807bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) 8817bc1ca39SPeng Fan 8827bc1ca39SPeng Fan /* MPWRDLCTL */ 8837bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) 8847bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) 8857bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) 8867bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) 8877bc1ca39SPeng Fan 8887bc1ca39SPeng Fan /* MPRDDLCTL */ 8897bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) 8907bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) 8917bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) 8927bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) 8937bc1ca39SPeng Fan 8947bc1ca39SPeng Fan /* MPWRDQBY0DL */ 8957bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) 8967bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) 8977bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) 8987bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) 8997bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) 9007bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) 9017bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) 9027bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) 9037bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) 9047bc1ca39SPeng Fan 9057bc1ca39SPeng Fan /* MPWRDQBY1DL */ 9067bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) 9077bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) 9087bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) 9097bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) 9107bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) 9117bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) 9127bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) 9137bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) 9147bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) 9157bc1ca39SPeng Fan 9167bc1ca39SPeng Fan /* MPWRDQBY2DL */ 9177bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) 9187bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) 9197bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) 9207bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) 9217bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) 9227bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) 9237bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) 9247bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) 9257bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) 9267bc1ca39SPeng Fan 9277bc1ca39SPeng Fan /* MPWRDQBY3DL */ 9287bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) 9297bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) 9307bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) 9317bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) 9327bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) 9337bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) 9347bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) 9357bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) 9367bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) 9377bc1ca39SPeng Fan 9387bc1ca39SPeng Fan #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 9397bc1ca39SPeng Fan 9407bc1ca39SPeng Fan #include <asm/types.h> 9417bc1ca39SPeng Fan 9427bc1ca39SPeng Fan struct fuse_word { 9437bc1ca39SPeng Fan u32 fuse; 9447bc1ca39SPeng Fan u32 rsvd[3]; 9457bc1ca39SPeng Fan }; 9467bc1ca39SPeng Fan 9477bc1ca39SPeng Fan struct ocotp_regs { 9487bc1ca39SPeng Fan u32 ctrl; 9497bc1ca39SPeng Fan u32 ctrl_set; 9507bc1ca39SPeng Fan u32 ctrl_clr; 9517bc1ca39SPeng Fan u32 ctrl_tog; 9527bc1ca39SPeng Fan u32 pdn; 9537bc1ca39SPeng Fan u32 rsvd0[3]; 9547bc1ca39SPeng Fan u32 data; 9557bc1ca39SPeng Fan u32 rsvd1[3]; 9567bc1ca39SPeng Fan u32 read_ctrl; 9577bc1ca39SPeng Fan u32 rsvd2[3]; 9587bc1ca39SPeng Fan u32 read_fuse_data; 9597bc1ca39SPeng Fan u32 rsvd3[3]; 9607bc1ca39SPeng Fan u32 sw_sticky; 9617bc1ca39SPeng Fan u32 rsvd4[3]; 9627bc1ca39SPeng Fan u32 scs; 9637bc1ca39SPeng Fan u32 scs_set; 9647bc1ca39SPeng Fan u32 scs_clr; 9657bc1ca39SPeng Fan u32 scs_tog; 9667bc1ca39SPeng Fan u32 out_status; 9677bc1ca39SPeng Fan u32 out_status_set; 9687bc1ca39SPeng Fan u32 out_status_clr; 9697bc1ca39SPeng Fan u32 out_status_tog; 9707bc1ca39SPeng Fan u32 startword; 9717bc1ca39SPeng Fan u32 rsvd5[3]; 9727bc1ca39SPeng Fan u32 version; 9737bc1ca39SPeng Fan u32 rsvd6[19]; 9747bc1ca39SPeng Fan struct fuse_word mem_repair[8]; 9757bc1ca39SPeng Fan u32 rsvd7[0xa8]; 9767bc1ca39SPeng Fan 9777bc1ca39SPeng Fan /* fuse banks */ 9787bc1ca39SPeng Fan struct fuse_bank { 9797bc1ca39SPeng Fan u32 fuse_regs[0x20]; 9807bc1ca39SPeng Fan } bank[0]; 9817bc1ca39SPeng Fan }; 9827bc1ca39SPeng Fan 9837bc1ca39SPeng Fan struct fuse_bank1_regs { 9847bc1ca39SPeng Fan u32 lock0; 9857bc1ca39SPeng Fan u32 rsvd0[3]; 9867bc1ca39SPeng Fan u32 lock1; 9877bc1ca39SPeng Fan u32 rsvd1[3]; 9887bc1ca39SPeng Fan u32 lock2; 9897bc1ca39SPeng Fan u32 rsvd2[3]; 9907bc1ca39SPeng Fan u32 cfg0; 9917bc1ca39SPeng Fan u32 rsvd3[3]; 9927bc1ca39SPeng Fan u32 cfg1; 9937bc1ca39SPeng Fan u32 rsvd4[3]; 9947bc1ca39SPeng Fan u32 cfg2; 9957bc1ca39SPeng Fan u32 rsvd5[3]; 9967bc1ca39SPeng Fan u32 cfg3; 9977bc1ca39SPeng Fan u32 rsvd6[3]; 9987bc1ca39SPeng Fan u32 cfg4; 9997bc1ca39SPeng Fan u32 rsvd7[3]; 10007bc1ca39SPeng Fan }; 10017bc1ca39SPeng Fan 10027bc1ca39SPeng Fan struct fuse_bank2_regs { 10037bc1ca39SPeng Fan struct fuse_word boot[8]; 10047bc1ca39SPeng Fan }; 10057bc1ca39SPeng Fan 10067bc1ca39SPeng Fan struct fuse_bank3_regs { 10077bc1ca39SPeng Fan u32 mem0; 10087bc1ca39SPeng Fan u32 rsvd0[3]; 10097bc1ca39SPeng Fan u32 mem1; 10107bc1ca39SPeng Fan u32 rsvd1[3]; 10117bc1ca39SPeng Fan u32 mem2; 10127bc1ca39SPeng Fan u32 rsvd2[3]; 10137bc1ca39SPeng Fan u32 mem3; 10147bc1ca39SPeng Fan u32 rsvd3[3]; 10157bc1ca39SPeng Fan u32 ana0; 10167bc1ca39SPeng Fan u32 rsvd4[3]; 10177bc1ca39SPeng Fan u32 ana1; 10187bc1ca39SPeng Fan u32 rsvd5[3]; 10197bc1ca39SPeng Fan u32 ana2; 10207bc1ca39SPeng Fan u32 rsvd6[3]; 10217bc1ca39SPeng Fan u32 ana3; 10227bc1ca39SPeng Fan u32 rsvd7[3]; 10237bc1ca39SPeng Fan }; 10247bc1ca39SPeng Fan 10257bc1ca39SPeng Fan struct fuse_bank7_regs { 10267bc1ca39SPeng Fan u32 sjc_resp0; 10277bc1ca39SPeng Fan u32 rsvd0[3]; 10287bc1ca39SPeng Fan u32 sjc_resp1; 10297bc1ca39SPeng Fan u32 rsvd1[3]; 10307bc1ca39SPeng Fan u32 gp0; 10317bc1ca39SPeng Fan u32 rsvd2[3]; 10327bc1ca39SPeng Fan u32 gp1; 10337bc1ca39SPeng Fan u32 rsvd3[3]; 10347bc1ca39SPeng Fan u32 gp2; 10357bc1ca39SPeng Fan u32 rsvd4[3]; 10367bc1ca39SPeng Fan u32 gp3; 10377bc1ca39SPeng Fan u32 rsvd5[3]; 10387bc1ca39SPeng Fan u32 gp4; 10397bc1ca39SPeng Fan u32 rsvd6[3]; 10407bc1ca39SPeng Fan u32 gp5; 10417bc1ca39SPeng Fan u32 rsvd7[3]; 10427bc1ca39SPeng Fan }; 10437bc1ca39SPeng Fan 10447bc1ca39SPeng Fan struct usbphy_regs { 10457bc1ca39SPeng Fan u32 usbphy_pwd; /* 0x000 */ 10467bc1ca39SPeng Fan u32 usbphy_pwd_set; /* 0x004 */ 10477bc1ca39SPeng Fan u32 usbphy_pwd_clr; /* 0x008 */ 10487bc1ca39SPeng Fan u32 usbphy_pwd_tog; /* 0x00c */ 10497bc1ca39SPeng Fan u32 usbphy_tx; /* 0x010 */ 10507bc1ca39SPeng Fan u32 usbphy_tx_set; /* 0x014 */ 10517bc1ca39SPeng Fan u32 usbphy_tx_clr; /* 0x018 */ 10527bc1ca39SPeng Fan u32 usbphy_tx_tog; /* 0x01c */ 10537bc1ca39SPeng Fan u32 usbphy_rx; /* 0x020 */ 10547bc1ca39SPeng Fan u32 usbphy_rx_set; /* 0x024 */ 10557bc1ca39SPeng Fan u32 usbphy_rx_clr; /* 0x028 */ 10567bc1ca39SPeng Fan u32 usbphy_rx_tog; /* 0x02c */ 10577bc1ca39SPeng Fan u32 usbphy_ctrl; /* 0x030 */ 10587bc1ca39SPeng Fan u32 usbphy_ctrl_set; /* 0x034 */ 10597bc1ca39SPeng Fan u32 usbphy_ctrl_clr; /* 0x038 */ 10607bc1ca39SPeng Fan u32 usbphy_ctrl_tog; /* 0x03c */ 10617bc1ca39SPeng Fan u32 usbphy_status; /* 0x040 */ 10627bc1ca39SPeng Fan u32 reserved0[3]; 10637bc1ca39SPeng Fan u32 usbphy_debug0; /* 0x050 */ 10647bc1ca39SPeng Fan u32 usbphy_debug0_set; /* 0x054 */ 10657bc1ca39SPeng Fan u32 usbphy_debug0_clr; /* 0x058 */ 10667bc1ca39SPeng Fan u32 usbphy_debug0_tog; /* 0x05c */ 10677bc1ca39SPeng Fan u32 reserved1[4]; 10687bc1ca39SPeng Fan u32 usbphy_debug1; /* 0x070 */ 10697bc1ca39SPeng Fan u32 usbphy_debug1_set; /* 0x074 */ 10707bc1ca39SPeng Fan u32 usbphy_debug1_clr; /* 0x078 */ 10717bc1ca39SPeng Fan u32 usbphy_debug1_tog; /* 0x07c */ 10727bc1ca39SPeng Fan u32 usbphy_version; /* 0x080 */ 10737bc1ca39SPeng Fan u32 reserved2[7]; 10747bc1ca39SPeng Fan u32 usb1_pll_480_ctrl; /* 0x0a0 */ 10757bc1ca39SPeng Fan u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ 10767bc1ca39SPeng Fan u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ 10777bc1ca39SPeng Fan u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ 10787bc1ca39SPeng Fan u32 reserved3[4]; 10797bc1ca39SPeng Fan u32 usb1_vbus_detect; /* 0xc0 */ 10807bc1ca39SPeng Fan u32 usb1_vbus_detect_set; /* 0xc4 */ 10817bc1ca39SPeng Fan u32 usb1_vbus_detect_clr; /* 0xc8 */ 10827bc1ca39SPeng Fan u32 usb1_vbus_detect_tog; /* 0xcc */ 10837bc1ca39SPeng Fan u32 usb1_vbus_det_stat; /* 0xd0 */ 10847bc1ca39SPeng Fan u32 reserved4[3]; 10857bc1ca39SPeng Fan u32 usb1_chrg_detect; /* 0xe0 */ 10867bc1ca39SPeng Fan u32 usb1_chrg_detect_set; /* 0xe4 */ 10877bc1ca39SPeng Fan u32 usb1_chrg_detect_clr; /* 0xe8 */ 10887bc1ca39SPeng Fan u32 usb1_chrg_detect_tog; /* 0xec */ 10897bc1ca39SPeng Fan u32 usb1_chrg_det_stat; /* 0xf0 */ 10907bc1ca39SPeng Fan u32 reserved5[3]; 10917bc1ca39SPeng Fan u32 usbphy_anactrl; /* 0x100 */ 10927bc1ca39SPeng Fan u32 usbphy_anactrl_set; /* 0x104 */ 10937bc1ca39SPeng Fan u32 usbphy_anactrl_clr; /* 0x108 */ 10947bc1ca39SPeng Fan u32 usbphy_anactrl_tog; /* 0x10c */ 10957bc1ca39SPeng Fan u32 usb1_loopback; /* 0x110 */ 10967bc1ca39SPeng Fan u32 usb1_loopback_set; /* 0x114 */ 10977bc1ca39SPeng Fan u32 usb1_loopback_clr; /* 0x118 */ 10987bc1ca39SPeng Fan u32 usb1_loopback_tog; /* 0x11c */ 10997bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt; /* 0x120 */ 11007bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt_set; /* 0x124 */ 11017bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ 11027bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ 11037bc1ca39SPeng Fan u32 usphy_trim_override_en; /* 0x130 */ 11047bc1ca39SPeng Fan u32 usphy_trim_override_en_set; /* 0x134 */ 11057bc1ca39SPeng Fan u32 usphy_trim_override_en_clr; /* 0x138 */ 11067bc1ca39SPeng Fan u32 usphy_trim_override_en_tog; /* 0x13c */ 11077bc1ca39SPeng Fan u32 usb1_pfda_ctrl1; /* 0x140 */ 11087bc1ca39SPeng Fan u32 usb1_pfda_ctrl1_set; /* 0x144 */ 11097bc1ca39SPeng Fan u32 usb1_pfda_ctrl1_clr; /* 0x148 */ 11107bc1ca39SPeng Fan u32 usb1_pfda_ctrl1_tog; /* 0x14c */ 11117bc1ca39SPeng Fan }; 11127bc1ca39SPeng Fan 11137bc1ca39SPeng Fan 11147bc1ca39SPeng Fan #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) 11157bc1ca39SPeng Fan #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) 11167bc1ca39SPeng Fan 11177bc1ca39SPeng Fan #endif 11187bc1ca39SPeng Fan 11197bc1ca39SPeng Fan #endif /* _MX7ULP_REGS_H_*/ 1120