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Searched refs:PCC1_RBASE (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dclock.c185 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT); in enable_ocotp_clk()
187 writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT)); in enable_ocotp_clk()
189 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT); in enable_ocotp_clk()
192 (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT)); in enable_ocotp_clk()
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h137 #define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) macro
201 #define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT))
202 #define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT))
211 #define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT))
214 #define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT))