Searched refs:PBS_RX_PHY_REG (Results 1 – 4 of 4) sorted by relevance
/openbmc/u-boot/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_centralization.c | 627 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx() 637 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx() 651 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx() 658 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx() 664 PBS_RX_PHY_REG(effective_cs, 5), in ddr3_tip_special_rx() 671 PBS_RX_PHY_REG(effective_cs, 5), in ddr3_tip_special_rx()
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H A D | ddr3_training_pbs.c | 776 PBS_RX_PHY_REG(effective_cs, 0) : in ddr3_tip_pbs() 944 PBS_RX_PHY_REG(cs_num, 0) : in ddr3_tip_print_pbs_result() 994 PBS_RX_PHY_REG(effective_cs, 0) : in ddr3_tip_clean_pbs_result()
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H A D | mv_ddr_regs.h | 455 #define PBS_RX_PHY_REG(cs, bit) (PBS_RX_PHY_BASE + (cs) * 0x10 + (bit)) macro
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H A D | ddr3_training.c | 1919 PBS_RX_PHY_REG(effective_cs, DQSP_PAD), 0)); in ddr3_tip_ddr3_reset_phy_regs() 1927 PBS_RX_PHY_REG(effective_cs, DQSN_PAD), 0)); in ddr3_tip_ddr3_reset_phy_regs()
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