Searched refs:PA_FPGA (Results 1 – 4 of 4) sorted by relevance
34 #define PA_FPGA (PA_PERIPHERAL + 0x01000000) macro39 #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */40 #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */41 #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */46 #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */47 #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */48 #define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */49 #define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */52 #define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */54 #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */[all …]
47 #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ macro50 #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */51 #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */52 #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */53 #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */58 #define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */61 #define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */62 #define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */64 #define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */65 #define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */[all …]
50 #define PA_FPGA 0xB7000000 /* FPGA base address */ macro54 #define FPGA_ILSR1 (PA_FPGA + 0x02)55 #define FPGA_ILSR2 (PA_FPGA + 0x03)56 #define FPGA_ILSR3 (PA_FPGA + 0x04)57 #define FPGA_ILSR4 (PA_FPGA + 0x05)58 #define FPGA_ILSR5 (PA_FPGA + 0x06)59 #define FPGA_ILSR6 (PA_FPGA + 0x07)60 #define FPGA_ILSR7 (PA_FPGA + 0x08)61 #define FPGA_ILSR8 (PA_FPGA + 0x09)
51 #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ macro