16a0abce4SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 */ 2939a24a6SPaul Mundt #ifndef __ASM_SH_SE7722_H 3939a24a6SPaul Mundt #define __ASM_SH_SE7722_H 4939a24a6SPaul Mundt 5939a24a6SPaul Mundt /* 6939a24a6SPaul Mundt * linux/include/asm-sh/se7722.h 7939a24a6SPaul Mundt * 8939a24a6SPaul Mundt * Copyright (C) 2007 Nobuhiro Iwamatsu 9939a24a6SPaul Mundt * 10939a24a6SPaul Mundt * Hitachi UL SolutionEngine 7722 Support. 11939a24a6SPaul Mundt */ 12b894701eSPaul Mundt #include <linux/sh_intc.h> 13939a24a6SPaul Mundt #include <asm/addrspace.h> 14939a24a6SPaul Mundt 15939a24a6SPaul Mundt /* Box specific addresses. */ 16939a24a6SPaul Mundt #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ 17939a24a6SPaul Mundt #define PA_ROM 0xa0000000 /* EPROM */ 18939a24a6SPaul Mundt #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ 19939a24a6SPaul Mundt #define PA_FROM 0xa1000000 /* Flash-ROM */ 20939a24a6SPaul Mundt #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ 21939a24a6SPaul Mundt #define PA_EXT1 0xa4000000 22939a24a6SPaul Mundt #define PA_EXT1_SIZE 0x04000000 23939a24a6SPaul Mundt #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ 24939a24a6SPaul Mundt #define PA_SDRAM_SIZE 0x04000000 25939a24a6SPaul Mundt 26939a24a6SPaul Mundt #define PA_EXT4 0xb0000000 27939a24a6SPaul Mundt #define PA_EXT4_SIZE 0x04000000 28939a24a6SPaul Mundt 29939a24a6SPaul Mundt #define PA_PERIPHERAL 0xB0000000 30939a24a6SPaul Mundt 31939a24a6SPaul Mundt #define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ 32939a24a6SPaul Mundt #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ 33939a24a6SPaul Mundt #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ 34939a24a6SPaul Mundt #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ 35939a24a6SPaul Mundt #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ 36939a24a6SPaul Mundt #define MRSHPC_OPTION (PA_MRSHPC + 6) 37939a24a6SPaul Mundt #define MRSHPC_CSR (PA_MRSHPC + 8) 38939a24a6SPaul Mundt #define MRSHPC_ISR (PA_MRSHPC + 10) 39939a24a6SPaul Mundt #define MRSHPC_ICR (PA_MRSHPC + 12) 40939a24a6SPaul Mundt #define MRSHPC_CPWCR (PA_MRSHPC + 14) 41939a24a6SPaul Mundt #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 42939a24a6SPaul Mundt #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 43939a24a6SPaul Mundt #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 44939a24a6SPaul Mundt #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 45939a24a6SPaul Mundt #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 46939a24a6SPaul Mundt #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 47939a24a6SPaul Mundt #define MRSHPC_CDCR (PA_MRSHPC + 28) 48939a24a6SPaul Mundt #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 49939a24a6SPaul Mundt 50939a24a6SPaul Mundt #define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ 51939a24a6SPaul Mundt #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ 52939a24a6SPaul Mundt 53939a24a6SPaul Mundt #define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ 54939a24a6SPaul Mundt /* GPIO */ 55939a24a6SPaul Mundt #define FPGA_IN 0xb1840000UL 56939a24a6SPaul Mundt #define FPGA_OUT 0xb1840004UL 57939a24a6SPaul Mundt 58939a24a6SPaul Mundt #define PORT_PECR 0xA4050108UL 59939a24a6SPaul Mundt #define PORT_PJCR 0xA4050110UL 60939a24a6SPaul Mundt #define PORT_PSELD 0xA4050154UL 61939a24a6SPaul Mundt #define PORT_PSELB 0xA4050150UL 62939a24a6SPaul Mundt 63939a24a6SPaul Mundt #define PORT_PSELC 0xA4050152UL 64939a24a6SPaul Mundt #define PORT_PKCR 0xA4050112UL 65939a24a6SPaul Mundt #define PORT_PHCR 0xA405010EUL 66939a24a6SPaul Mundt #define PORT_PLCR 0xA4050114UL 67939a24a6SPaul Mundt #define PORT_PMCR 0xA4050116UL 68939a24a6SPaul Mundt #define PORT_PRCR 0xA405011CUL 69939a24a6SPaul Mundt #define PORT_PXCR 0xA4050148UL 70939a24a6SPaul Mundt #define PORT_PSELA 0xA405014EUL 71939a24a6SPaul Mundt #define PORT_PYCR 0xA405014AUL 72939a24a6SPaul Mundt #define PORT_PZCR 0xA405014CUL 73939a24a6SPaul Mundt #define PORT_HIZCRA 0xA4050158UL 74939a24a6SPaul Mundt #define PORT_HIZCRC 0xA405015CUL 75939a24a6SPaul Mundt 76939a24a6SPaul Mundt /* IRQ */ 77b894701eSPaul Mundt #define IRQ0_IRQ evt2irq(0x600) 78b894701eSPaul Mundt #define IRQ1_IRQ evt2irq(0x620) 79939a24a6SPaul Mundt 80939a24a6SPaul Mundt #define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ 81939a24a6SPaul Mundt #define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ 82939a24a6SPaul Mundt #define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ 83939a24a6SPaul Mundt #define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ 84939a24a6SPaul Mundt #define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ 85939a24a6SPaul Mundt #define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ 86939a24a6SPaul Mundt #define SE7722_FPGA_IRQ_NR 6 87939a24a6SPaul Mundt 885df38b9bSPaul Mundt struct irq_domain; 895df38b9bSPaul Mundt 90939a24a6SPaul Mundt /* arch/sh/boards/se/7722/irq.c */ 915df38b9bSPaul Mundt extern struct irq_domain *se7722_irq_domain; 92a37c6c7aSPaul Mundt 93939a24a6SPaul Mundt void init_se7722_IRQ(void); 94939a24a6SPaul Mundt 95939a24a6SPaul Mundt #define __IO_PREFIX se7722 96939a24a6SPaul Mundt #include <asm/io_generic.h> 97939a24a6SPaul Mundt 98939a24a6SPaul Mundt #endif /* __ASM_SH_SE7722_H */ 99