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Searched refs:PACKET3_SET_CONTEXT_REG (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h262 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dnvd.h321 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dsoc15d.h296 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dvid.h342 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dcikd.h460 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dgfx_v7_0.c2489 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_cp_gfx_start()
2497 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
2508 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
3937 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_get_csb_buffer()
3947 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_get_csb_buffer()
H A Dgfx_v6_0.c2024 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_cp_gfx_start()
2038 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v6_0_cp_gfx_start()
2859 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_get_csb_buffer()
2869 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v6_0_get_csb_buffer()
H A Dsid.h1848 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dgfx_v11_0.c637 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v11_0_get_csb_buffer()
650 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v11_0_get_csb_buffer()
3160 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v11_0_cp_gfx_start()
3172 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v11_0_cp_gfx_start()
H A Dgfx_v8_0.c1233 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1244 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
4172 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v8_0_cp_gfx_start()
4182 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_cp_gfx_start()
H A Dgfx_v10_0.c4094 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v10_0_get_csb_buffer()
4107 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v10_0_get_csb_buffer()
5979 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v10_0_cp_gfx_start()
5991 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v10_0_cp_gfx_start()
H A Dgfx_v9_0.c1464 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v9_0_get_csb_buffer()
3065 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v9_0_cp_gfx_start()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dnid.h1272 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dsi.c3604 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in si_cp_start()
4575 case PACKET3_SET_CONTEXT_REG: in si_vm_packet3_gfx_check()
4678 case PACKET3_SET_CONTEXT_REG: in si_vm_packet3_compute_check()
5736 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in si_get_csb_buffer()
5746 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in si_get_csb_buffer()
H A Dsid.h1785 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dcikd.h1928 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Devergreen_cs.c2316 case PACKET3_SET_CONTEXT_REG: in evergreen_packet3_check()
3395 case PACKET3_SET_CONTEXT_REG: in evergreen_vm_packet3_check()
H A Devergreend.h1668 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dr600d.h1689 #define PACKET3_SET_CONTEXT_REG 0x69 macro
H A Dr600_cs.c1924 case PACKET3_SET_CONTEXT_REG: in r600_packet3_check()
H A Dcik.c4013 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
6721 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in cik_get_csb_buffer()
6731 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_get_csb_buffer()