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Searched refs:PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h253 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dsoc15d.h216 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dnvd.h206 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dvid.h268 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dcikd.h386 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dsid.h1839 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dgfx_v6_0.c2018 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()
2850 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
H A Dgfx_v7_0.c2479 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
3927 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
H A Dgfx_v11_0.c627 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_get_csb_buffer()
3150 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_cp_gfx_start()
H A Dgfx_v8_0.c1223 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4162 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
H A Dgfx_v9_0.c1454 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
3055 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
H A Dgfx_v10_0.c4084 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()
5969 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dnid.h1262 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dsid.h1776 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dcikd.h1854 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Devergreend.h1657 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dni.c1566 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
H A Dsi.c3592 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_cp_start()
5726 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_get_csb_buffer()
H A Dcik.c3997 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
6711 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_get_csb_buffer()
H A Devergreen.c3030 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in evergreen_cp_start()