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Searched refs:OSCR (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/clocksource/
H A Dtimer-pxa.c31 #define OSCR 0x10 /* OS Timer Counter Register */ macro
59 return timer_readl(OSCR); in pxa_read_sched_clock()
84 next = timer_readl(OSCR) + delta; in pxa_osmr0_set_next_event()
86 oscr = timer_readl(OSCR); in pxa_osmr0_set_next_event()
109 oscr = timer_readl(OSCR); in pxa_timer_suspend()
128 timer_writel(oscr, OSCR); in pxa_timer_resume()
164 ret = clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200, in pxa_timer_common_init()
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A Dmtd-xip.h20 #define xip_currtime() readl_relaxed(OSCR)
21 #define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
H A DSA-1100.h838 #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ macro
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dpxa2xx.c44 writel(0, OSCR); in pxa_wait_ticks()
45 while (readl(OSCR) < ticks) in pxa_wait_ticks()
278 tmp = readl(OSCR); in reset_cpu()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dconfig.h22 #define CONFIG_SYS_TIMER_COUNTER OSCR
H A Dpxa-regs.h923 #define OSCR 0x40A00010 /* OS Timer Counter Register */ macro
/openbmc/linux/arch/arm/mach-pxa/
H A Dregs-ost.h18 #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ macro
H A Dreset.c78 writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3); in do_hw_reset()
/openbmc/u-boot/arch/arm/cpu/sa1100/
H A Dtimer.c17 return OSCR; in get_timer_masked()
/openbmc/qemu/hw/timer/
H A Dpxa2xx_timer.c34 #define OSCR 0x10 /* OS Timer Count */ macro
194 case OSCR: in pxa2xx_timer_read()
308 case OSCR: in pxa2xx_timer_write()
/openbmc/u-boot/include/
H A DSA-1100.h1132 #define OSCR /* OS timer Counter Reg. */ \ macro