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Searched refs:ORIG_REG (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.inc68 #define fSAT_ORIG_SHL(A, ORIG_REG) \
69 (((fCAST4s((fSAT(A)) ^ (fCAST4s(ORIG_REG)))) < 0) \
70 ? fSATVALN(32, (fCAST4s(ORIG_REG))) \
71 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
/openbmc/qemu/target/hexagon/
H A Dmacros.h476 #define fSAT_ORIG_SHL(A, ORIG_REG) \ argument
477 ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
478 ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
479 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
/openbmc/qemu/target/hexagon/imported/
H A Dmacros.def967 ((((size4s_t)((fSAT(A)) ^ ((size4s_t)(ORIG_REG)))) < 0) ?
968 fSATVALN(32,((size4s_t)(ORIG_REG))) :
969 ((((ORIG_REG) > 0) && ((A) == 0)) ?
970 fSATVALN(32,(ORIG_REG)) :