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Searched refs:OPER_WRITE (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_bist.c47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
H A Dddr3_training_ip_engine.c401 tx_burst_size = (direction == OPER_WRITE) ? in ddr3_tip_ip_training()
403 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0; in ddr3_tip_ip_training()
404 rd_mode = (direction == OPER_WRITE) ? 1 : 0; in ddr3_tip_ip_training()
463 direction == OPER_WRITE) { in ddr3_tip_ip_training()
466 direction == OPER_WRITE) { in ddr3_tip_ip_training()
481 direction == OPER_WRITE) { in ddr3_tip_ip_training()
1111 u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0); in ddr3_tip_ip_training_wrapper()
1354 if ((byte_status[if_id][sybphy_id] != BYTE_NOT_DEFINED) && (direction == OPER_WRITE)) { in ddr3_tip_ip_training_wrapper()
H A Dddr3_training_ip_def.h125 OPER_WRITE, enumerator
H A Dddr3_training_centralization.c95 direction = OPER_WRITE; in ddr3_tip_centralization()
392 OPER_WRITE) { in ddr3_tip_centralization()
H A Dddr3_training_pbs.c43 enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE; in ddr3_tip_pbs()