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Searched refs:OPCODE_REG1_REG (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h28 #define OPCODE_REG1_REG(obj) (OPCODE_REG1_BASE + (obj) * 0x4) macro
H A Dddr3_training_leveling.c133 OPCODE_REG1_REG(1), 0xd00, 0xd00)); in ddr3_tip_dynamic_read_leveling()
505 OPCODE_REG1_REG(1), 0xd00, 0xd00)); in ddr3_tip_dynamic_per_bit_read_leveling()
1485 OPCODE_REG1_REG(1), 0x80, 0xffff)); in ddr3_tip_dynamic_write_leveling_seq()
H A Dddr3_training_ip_engine.c453 OPCODE_REG1_REG(1), num_iter, in ddr3_tip_ip_training()