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Searched refs:OMAP3430_GR_MOD (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/arm/mach-omap2/
H A Dprm3xxx.h45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
51 #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
53 #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
55 #define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
57 #define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
61 #define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
63 #define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
65 #define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
67 #define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
77 #define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
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H A Dprm3xxx.c118 return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); in omap3_prm_vcvp_read()
123 omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); in omap3_prm_vcvp_write()
128 return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); in omap3_prm_vcvp_rmw()
140 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, in omap3xxx_prm_dpll3_reset()
143 omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL); in omap3xxx_prm_dpll3_reset()
300 OMAP3430_GR_MOD, in omap3_prm_init_pm()
515 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & in omap3xxx_prm_clear_global_cold_reset()
518 OMAP3430_GR_MOD, in omap3xxx_prm_clear_global_cold_reset()
528 *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, in omap3_prm_save_scratchpad_contents()
531 *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, in omap3_prm_save_scratchpad_contents()
H A Dprcm-common.h44 #define OMAP3430_GR_MOD 0xa00 macro