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Searched refs:ODPG_WR_RD_MODE_ENA_REG (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h34 #define ODPG_WR_RD_MODE_ENA_REG 0x10fc macro
H A Dddr3_training_leveling.c109 ODPG_WR_RD_MODE_ENA_REG, 0, in ddr3_tip_dynamic_read_leveling()
483 ODPG_WR_RD_MODE_ENA_REG, 0, in ddr3_tip_dynamic_per_bit_read_leveling()
H A Dddr3_training_pbs.c878 ODPG_WR_RD_MODE_ENA_REG, 0xffff, MASK_ALL_BITS)); in ddr3_tip_pbs()
H A Dddr3_training_ip_engine.c415 ODPG_WR_RD_MODE_ENA_REG, reg_data, in ddr3_tip_ip_training()
H A Dddr3_training.c1961 ODPG_WR_RD_MODE_ENA_REG, in ddr3_tip_restore_dunit_regs()