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Searched refs:ODPG_DATA_CTRL_REG (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_bist.c34 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
39 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
66 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_bist_activate()
434 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_bist_tx()
452 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in mv_ddr_odpg_bist_prepare()
457 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in mv_ddr_odpg_bist_prepare()
507 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_dm_vw_get()
526 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
531 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
559 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
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H A Dddr3_training_ip_engine.c384 ODPG_DATA_CTRL_REG, in ddr3_tip_ip_training()
393 ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26, in ddr3_tip_ip_training()
563 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_ip_training()
639 ODPG_DATA_CTRL_REG, data_value, 0xaffffffc); in ddr3_tip_configure_odpg()
722 ODPG_DATA_CTRL_REG, (cs_num_type << 26), (3 << 26))); in ddr3_tip_read_training_result()
893 ODPG_DATA_CTRL_REG, reg_data, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
897 ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
922 ODPG_DATA_CTRL_REG, (u32)(0x1 << 31), in ddr3_tip_load_pattern_to_mem()
933 ODPG_DATA_CTRL_REG, (0x1 << 30), (u32) (0x3 << 30))); in ddr3_tip_load_pattern_to_mem()
938 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
H A Dddr3_training_leveling.c89 ODPG_DATA_CTRL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_read_leveling()
196 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_read_leveling()
253 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
262 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
463 ODPG_DATA_CTRL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_per_bit_read_leveling()
568 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_per_bit_read_leveling()
732 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
740 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
1735 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, in mv_ddr_rl_dqs_burst()
H A Dmv_ddr_regs.h279 #define ODPG_DATA_CTRL_REG 0x1630 macro