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Searched refs:NUM_DISPCLK_DPM_LEVELS (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h44 #define NUM_DISPCLK_DPM_LEVELS 4 macro
112 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
H A Dsmu13_driver_if_yellow_carp.h104 #define NUM_DISPCLK_DPM_LEVELS 8 macro
123 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
H A Dsmu11_driver_if_vangogh.h104 #define NUM_DISPCLK_DPM_LEVELS 7 macro
129 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
H A Dsmu13_driver_if_v13_0_4.h105 #define NUM_DISPCLK_DPM_LEVELS 8 macro
124 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
H A Dsmu11_driver_if_navi10.h43 #define NUM_DISPCLK_DPM_LEVELS 8 macro
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
591 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
H A Dsmu11_driver_if_sienna_cichlid.h42 #define NUM_DISPCLK_DPM_LEVELS 8 macro
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
687 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
1047 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
H A Dsmu13_driver_if_v13_0_7.h38 #define NUM_DISPCLK_DPM_LEVELS 8 macro
1055 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
1399 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
H A Dsmu13_driver_if_v13_0_0.h37 #define NUM_DISPCLK_DPM_LEVELS 8 macro
1046 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
1406 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h33 #define NUM_DISPCLK_DPM_LEVELS 4 macro
71 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h33 #define NUM_DISPCLK_DPM_LEVELS 8 macro
79 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
H A Ddcn316_clk_mgr.c508 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn316_clk_mgr_helper_populate_bw_params()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h106 #define NUM_DISPCLK_DPM_LEVELS 8 macro
132 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
H A Ddcn31_clk_mgr.c585 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h51 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
H A Ddcn314_clk_mgr.c589 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()
653 …table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS); in dcn314_clk_mgr_helper_populate_bw_params()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h43 #define NUM_DISPCLK_DPM_LEVELS 8 macro
56 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
315 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu11_driver_if.h45 #define NUM_DISPCLK_DPM_LEVELS 8 macro
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
428 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_processpptables.c344 for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)