Searched refs:M_REG_S (Results 1 – 9 of 9) sorted by relevance
68 value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; in arm_v7m_mrs_control()368 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER()369 bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); in HELPER()374 bool ts = is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); in HELPER()386 armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); in HELPER()387 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in HELPER()586 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in HELPER()631 if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) { in HELPER()649 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in HELPER()776 bool priv = !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_NPRIV_MASK) || in v7m_push_callee_stack()[all …]
133 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM()134 sfpa = load_cpu_field(v7m.control[M_REG_S]); in trans_VSCCLRM()297 fpca = load_cpu_field(v7m.control[M_REG_S]); in gen_branch_fpInactive()389 control = load_cpu_field(v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()392 store_cpu_field(control, v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()480 control = load_cpu_field(v7m.control[M_REG_S]); in gen_M_fp_sysreg_read()494 store_cpu_field(control, v7m.control[M_REG_S]); in gen_M_fp_sysreg_read()533 control = load_cpu_field(v7m.control[M_REG_S]); in gen_M_fp_sysreg_read()
161 tmp = load_cpu_field(v7m.fpccr[M_REG_S]); in gen_update_fp_context()167 store_cpu_field(tmp, v7m.fpccr[M_REG_S]); in gen_update_fp_context()202 control = load_cpu_field(v7m.control[M_REG_S]); in gen_update_fp_context()204 store_cpu_field(control, v7m.control[M_REG_S]); in gen_update_fp_context()
414 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; in csselr_vmstate_validate()677 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; in s_rnr_vmstate_validate()704 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),705 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),706 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),707 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),708 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),709 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),710 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),711 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion,[all …]
408 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold() 435 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold() 439 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold() 443 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; in arm_cpu_reset_hold() 448 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | in arm_cpu_reset_hold() 456 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; in arm_cpu_reset_hold() 494 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset_hold() 496 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; in arm_cpu_reset_hold() 516 memset(env->pmsav8.rbar[M_REG_S], 0, in arm_cpu_reset_hold() 517 sizeof(*env->pmsav8.rbar[M_REG_S]) in arm_cpu_reset_hold() [all...]
59 M_REG_S = 1, enumerator
12911 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) in arm_security_space_below_el3() 12917 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || in arm_security_space_below_el3() 12919 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { in arm_security_space_below_el3() 12928 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in arm_security_space_below_el3()
476 &s->systick[M_REG_S], TYPE_SYSTICK); in armv7m_realize()478 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk", in armv7m_realize()481 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk", in armv7m_realize()484 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { in armv7m_realize()487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, in armv7m_realize()489 "systick-trigger", M_REG_S)); in armv7m_realize()
246 for (bank = M_REG_S; bank >= M_REG_NS; bank--) { in nvic_recompute_state_secure()251 if (bank == M_REG_S) { in nvic_recompute_state_secure()270 pending_is_s_banked = (bank == M_REG_S); in nvic_recompute_state_secure()351 if (env->v7m.basepri[M_REG_S] > 0) { in nvic_exec_prio()352 int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S); in nvic_exec_prio()368 if (env->v7m.primask[M_REG_S]) { in nvic_exec_prio()386 if (env->v7m.faultmask[M_REG_S]) { in nvic_exec_prio()691 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp()1508 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl()1516 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl()[all …]