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Searched refs:M_REG_NS (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/target/arm/
H A Dmachine.c395 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU),
396 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
413 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK in csselr_vmstate_validate()
442 VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU),
518 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
519 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
520 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
521 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU),
522 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),
525 VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),
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H A Dcpu-qom.h58 M_REG_NS = 0, enumerator
H A Dcpu.c407 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
434 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
438 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold()
442 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; in arm_cpu_reset_hold()
447 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; in arm_cpu_reset_hold()
457 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; in arm_cpu_reset_hold()
493 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; in arm_cpu_reset_hold()
509 memset(env->pmsav8.rbar[M_REG_NS], 0, in arm_cpu_reset_hold()
510 sizeof(*env->pmsav8.rbar[M_REG_NS]) in arm_cpu_reset_hold()
512 memset(env->pmsav8.rlar[M_REG_NS], in arm_cpu_reset_hold()
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H A Dhelper.c4168 u32p += env->pmsav7.rnr[M_REG_NS];
4182 u32p += env->pmsav7.rnr[M_REG_NS]; in pmsav8r_regn_write()
4209 env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in pmsav8r_regn_read()
4214 return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; in pmsav8r_regn_read()
4223 env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in pmsav8r_regn_read()
4228 return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
[all...]
/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c264 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; in v7m_stack_write()
267 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; in v7m_stack_write()
338 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_UNSTKERR_MASK; in v7m_stack_read()
996 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr()
1448 env->v7m.faultmask[M_REG_NS] = 0; in do_v7m_exception_exit()
2022 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; in v7m_read_half_insn()
2072 env->v7m.cfsr[M_REG_NS] |= in v7m_read_sg_stack_word()
2301 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; in arm_v7m_cpu_do_interrupt()
2305 env->v7m.cfsr[M_REG_NS] |= in arm_v7m_cpu_do_interrupt()
2409 if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { in arm_v7m_cpu_do_interrupt()
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H A Dtranslate-m-nocp.c296 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive()
495 fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
509 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
540 fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
/openbmc/qemu/hw/arm/
H A Darmv7m.c264 object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS], in armv7m_instance_init()
458 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", in armv7m_realize()
461 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk); in armv7m_realize()
462 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { in armv7m_realize()
465 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, in armv7m_realize()
467 "systick-trigger", M_REG_NS)); in armv7m_realize()
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c246 for (bank = M_REG_S; bank >= M_REG_NS; bank--) { in nvic_recompute_state_secure()
347 if (env->v7m.basepri[M_REG_NS] > 0) { in nvic_exec_prio()
348 running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS); in nvic_exec_prio()
358 if (env->v7m.primask[M_REG_NS]) { in nvic_exec_prio()
372 if (env->v7m.faultmask[M_REG_NS]) { in nvic_exec_prio()
1113 val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; in nvic_readl()
1527 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl()
1693 cpu->env.v7m.ccr[M_REG_NS] = in nvic_writel()
1694 (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) in nvic_writel()
1704 value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; in nvic_writel()
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