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Searched refs:MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.h77 #define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT 0xDD301007 macro
H A Dddr3_init.c288 if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT) in ddr3_init()
H A Dddr3_spd.c684 return MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT;