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Searched refs:MUX (Results 1 – 17 of 17) sorted by relevance

/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dpl-Warszawa5 [Raszyn/PKiN MUX-3]
17 [Raszyn/PKiN MUX-8 (TVNHD)]
29 [Raszyn/PKiN MUX-1]
41 [Raszyn/PKiN MUX-2]
53 [PKiN MUX-8]
H A Dpl-Czestochowa11 [MUX-1 Emitel Wreczyca 100KW H]
23 [MUX-2 Emitel Wreczyca 100KW H]
35 [MUX-3 TON Czestochowa/Bleszno 2KW H]
H A Dee-All4 # Additional MUX info http://www.levira.ee/program.pdf
/openbmc/u-boot/drivers/i2c/muxes/
H A DKconfig8 using a suitable I2C MUX driver.
17 using a suitable I2C MUX driver.
44 I2C busses connected through a MUX, which is controlled
/openbmc/docs/designs/
H A Dmultihost-phosphor-buttons.md16 form factor inputs such as switches/MUX other than push type buttons are needed
28 corresponding to platform specific hardware buttons/MUX/Switches which are
122 ## 2.Serial console MUX switch
124 There is also uart console for each host and bmc which is connected via a MUX
128 the console which is based on the UART MUX switch configuration.
159 changes (needed for serial console MUX).
210 ## serial console MUX interface
H A Duart-mux-support.md407 | console | | MUX |
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt60 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
61 The MUX 0 means gpio and MUX 1 to N mean the specific device function.
/openbmc/openbmc/meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/
H A Dyosemite4.cfg31 # MUX controller for setting UART switch mode
/openbmc/u-boot/arch/arm/dts/
H A Darmada-385-atl-x530.dtsi144 i2c@0 { /* POE devices MUX */
204 sfpmux: mux@77 { /* SFP I2C MUX */
/openbmc/u-boot/doc/
H A DREADME.fsl-hwconfig12 12.288MHz. This option has two effects. First, the MUX on the board
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.h129 #define MUX(_id, _parents, _reg, _shift, _width) { \ macro
H A Dclk-mt7623.c567 MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
569 MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
570 MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
571 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
/openbmc/obmc-console/docs/
H A Dmux-support.md7 a mux. GPIO `UART-MUX-CTL` can be used to select one. This scenario is shown in
173 | console | | MUX |
/openbmc/qemu/target/hexagon/imported/
H A Dcompare.idef214 "Scalar MUX",
271 "Scalar MUX immediates",
277 "Scalar MUX register immediate",
282 "Scalar MUX register immediate",
288 "Vector MUX",
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg37 # bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
/openbmc/phosphor-buttons/
H A DREADME.md300 The other gpios part of the group gpio config is serial uart MUX gpio select
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig342 bool "Workaround for PIN MUX erratum A010539"