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Searched refs:MSTPCR2 (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7724.c28 #define MSTPCR2 0xa4150038 macro
234 [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
235 [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
249 [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
250 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
251 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
252 [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
253 [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
254 [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
255 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
[all …]
H A Dclock-sh7723.c27 #define MSTPCR2 0xa4150038 macro
173 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
184 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
185 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
186 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
187 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
188 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
189 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
190 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
[all …]
H A Dclock-sh7343.c23 #define MSTPCR2 0xa4150038 macro
166 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
167 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
168 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
169 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
171 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
175 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
177 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
178 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
179 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
[all …]
H A Dclock-sh7366.c23 #define MSTPCR2 0xa4150038 macro
166 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
167 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
168 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
169 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
170 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
171 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
175 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
176 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
177 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
[all …]
H A Dclock-sh7722.c26 #define MSTPCR2 0xa4150038 macro
156 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
158 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
159 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
160 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
161 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
162 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
163 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
164 [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
165 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
[all …]
H A Dclock-sh7757.c77 #define MSTPCR2 0xffc10028 macro
99 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
/openbmc/linux/arch/sh/boot/romimage/
H A Dmmcif-sh7724.c16 #define MSTPCR2 0xa4150038 macro
42 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader()
75 __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); in mmcif_loader()
/openbmc/u-boot/board/renesas/ecovec/
H A Decovec.c47 outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); in board_late_init()
89 outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); in board_init()
/openbmc/linux/arch/sh/include/cpu-sh4/cpu/
H A Dfreq.h21 #define MSTPCR2 0xa4150038 macro
45 #define MSTPCR2 0xa4150038 macro
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7723.h76 #define MSTPCR2 0xA4150038 macro
H A Dcpu_sh7724.h97 #define MSTPCR2 0xA4150038 macro
H A Dcpu_sh7722.h205 #define MSTPCR2 0xA4150038 macro
/openbmc/u-boot/board/renesas/ap325rxa/
H A Dap325rxa.c94 outl(MSTPCR2_D, MSTPCR2); in board_init()
/openbmc/u-boot/board/ms7722se/
H A Dlowlevel_init.S136 MSTPCR2_A: .long MSTPCR2
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S122 MSTPCR2_A: .long MSTPCR2