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Searched refs:MSTPCR0 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7786.c79 #define MSTPCR0 0xffc40030 macro
92 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
93 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
94 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
95 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
96 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
108 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
109 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
110 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
111 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
[all …]
H A Dclock-sh7723.c25 #define MSTPCR0 0xa4150030 macro
155 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
156 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
160 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
161 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
162 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
163 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
164 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
165 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
166 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
[all …]
H A Dclock-sh7785.c80 #define MSTPCR0 0xffc80030 macro
91 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
92 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
93 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
94 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
95 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
96 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
103 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
104 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
105 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
[all …]
H A Dclock-sh7343.c21 #define MSTPCR0 0xa4150030 macro
144 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
151 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
152 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
155 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
156 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
157 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
158 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
159 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
160 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
[all …]
H A Dclock-sh7366.c21 #define MSTPCR0 0xa4150030 macro
147 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
148 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
149 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
154 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
155 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
158 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
159 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
160 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
161 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
[all …]
H A Dclock-sh7724.c26 #define MSTPCR0 0xa4150030 macro
216 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
217 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
220 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
221 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
222 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
223 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
224 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
225 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
226 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
[all …]
H A Dclock-sh7734.c81 #define MSTPCR0 0xFFC80030 macro
126 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
127 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
128 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
129 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
130 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
131 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
132 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
141 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
142 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
[all …]
H A Dclock-shx3.c73 #define MSTPCR0 0xffc00030 macro
83 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
84 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
85 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
86 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
87 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
88 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
89 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
90 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
91 [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
[all …]
H A Dclock-sh7722.c24 #define MSTPCR0 0xa4150030 macro
142 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
143 [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
144 [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
145 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
146 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
147 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
148 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
149 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
150 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
H A Dclock-sh7757.c75 #define MSTPCR0 0xffc80030 macro
85 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
86 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
/openbmc/linux/arch/sh/include/cpu-sh4/cpu/
H A Dfreq.h19 #define MSTPCR0 0xa4150030 macro
43 #define MSTPCR0 0xa4150030 macro
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7723.h74 #define MSTPCR0 0xA4150030 macro
H A Dcpu_sh7724.h95 #define MSTPCR0 0xA4150030 macro
H A Dcpu_sh7722.h203 #define MSTPCR0 0xA4150030 macro
/openbmc/u-boot/board/ms7722se/
H A Dlowlevel_init.S135 MSTPCR0_A: .long MSTPCR0
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S121 MSTPCR0_A: .long MSTPCR0