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Searched refs:MSS (Results 1 – 25 of 31) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,msm8996-mss-pil.yaml27 - description: MSS QDSP6 registers
114 within MSS.
216 - description: GCC MSS IFACE clock
217 - description: GCC MSS BUS clock
218 - description: GCC MSS MEM clock
220 - description: GCC MSS GPLL0 clock
256 - description: GCC MSS BUS clock
257 - description: GCC MSS MEM clock
293 - description: GCC MSS BUS clock
294 - description: GCC MSS MEM clock
[all …]
H A Dqcom,sc7180-mss-pil.yaml7 title: Qualcomm SC7180 MSS Peripheral Image Loader
23 - description: MSS QDSP6 registers
56 - description: GCC MSS IFACE clock
57 - description: GCC MSS BUS clock
58 - description: GCC MSS NAV clock
59 - description: GCC MSS SNOC_AXI clock
60 - description: GCC MSS MFAB_AXIS clock
76 - description: MSS power domain
110 within MSS.
152 - description: IRQ from MSS to GLINK
[all …]
H A Dqcom,sc7280-mss-pil.yaml7 title: Qualcomm SC7280 MSS Peripheral Image Loader
23 - description: MSS QDSP6 registers
60 - description: GCC MSS IFACE clock
61 - description: GCC MSS OFFLINE clock
62 - description: GCC MSS SNOC_AXI clock
77 - description: MSS power domain
110 within MSS.
166 - description: IRQ from MSS to GLINK
170 - description: Mailbox for communication between APPS and MSS
H A Dqcom,msm8916-mss-pil.yaml7 title: Qualcomm MSM8916 MSS Peripheral Image Loader (and similar)
31 - description: MSS QDSP6 registers
73 - description: MSS proxy power domain (control handed over after startup)
88 description: MSS power domain supply (only valid for qcom,msm8974-mss-pil)
92 - description: MSS restart control
113 within MSS.
H A Dqcom,sdx55-pas.yaml41 - description: MSS power domain
H A Dqcom,sc7180-pas.yaml44 - description: MSS power domain
H A Dqcom,sm6350-pas.yaml116 - description: MSS power domain
H A Dqcom,sm8150-pas.yaml108 - description: MSS power domain
H A Dqcom,sm8550-pas.yaml109 - description: MSS power domain
H A Dqcom,sm8350-pas.yaml94 - description: MSS power domain
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-protocols/rp-pppoe/rp-pppoe/
H A Dpppoe-server.init9 if [ -n "$MSS" ]; then
10 OPTIONS="$OPTIONS -m $MSS"
H A Dpppoe-server.default4 #MSS=1412
/openbmc/linux/tools/testing/selftests/net/
H A Dgro.c70 #define MSS (4096 - sizeof(struct tcphdr) - sizeof(struct ipv6hdr)) macro
72 #define NUM_LARGE_PKT (MAX_PAYLOAD / MSS)
348 static char pkts[NUM_LARGE_PKT][TOTAL_HDR_LEN + MSS]; in send_large()
349 static char last[TOTAL_HDR_LEN + MSS]; in send_large()
350 static char new_seg[TOTAL_HDR_LEN + MSS]; in send_large()
354 create_packet(pkts[i], i * MSS, 0, MSS, 0); in send_large()
355 create_packet(last, NUM_LARGE_PKT * MSS, 0, remainder, 0); in send_large()
356 create_packet(new_seg, (NUM_LARGE_PKT + 1) * MSS, 0, remainder, 0); in send_large()
359 write_packet(fd, pkts[i], total_hdr_len + MSS, daddr); in send_large()
892 int remainder = (MAX_PAYLOAD + offset) % MSS; in gro_sender()
[all …]
/openbmc/qemu/docs/system/s390x/
H A Dcss.rst6 devices passed via vfio-ccw). It supports multiple subchannel sets (MSS) and
20 does not enable MSS (any Linux version that supports virtio also enables MSS).
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dmicrochip,mpfs-mailbox.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
/openbmc/linux/drivers/staging/most/dim2/
H A Dreg.h22 u32 MSS; /* 0x08 */ member
/openbmc/linux/Documentation/devicetree/bindings/soc/microchip/
H A Dmicrochip,mpfs-sys-controller.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
/openbmc/u-boot/arch/arm/dts/
H A Darmada-8040-mcbin.dts85 * [33] MSS power down
87 * [39] MSS CKE Enable
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dap80x-system-controller.txt27 - 3: MSS clock, derived from the fixed PLL
/openbmc/linux/Documentation/networking/
H A Dsegmentation-offloads.rst113 out over multiple skbuffs that have been resized to match the MSS provided
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8998-oneplus-common.dtsi570 /* Leave disabled until MSS is functional */
/openbmc/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_main.c254 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3)); in xgene_enet_tx_completion()
360 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); in xgene_enet_work_msg()
/openbmc/linux/arch/arm64/tools/
H A Dsysreg1905 Field 15:0 MSS
2595 Field 15:0 MSS
/openbmc/linux/drivers/net/ethernet/chelsio/inline_crypto/chtls/
H A Dchtls_io.c192 FLOWC_PARAM(MSS, tp->mss_cache); in send_tx_flowc_wr()
/openbmc/linux/net/netfilter/
H A DKconfig1127 MSS value of TCP SYN packets, to control the maximum size for that
1630 MSS value of TCP SYN packets, which control the maximum packet size

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