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Searched refs:MSR_IA32_RTIT_ADDR0_A (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h308 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 macro
/openbmc/linux/arch/x86/include/asm/
H A Dmsr-index.h324 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 macro
/openbmc/linux/arch/x86/kvm/vmx/
H A Dvmx.c704 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: in is_valid_passthrough_msr()
1212 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); in pt_load_msr()
1226 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); in pt_save_msr()
2117 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: in vmx_get_msr()
2118 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; in vmx_get_msr()
2423 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: in vmx_set_msr()
2426 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; in vmx_set_msr()
4117 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
/openbmc/linux/arch/x86/events/intel/
H A Dpt.c437 .msr_a = MSR_IA32_RTIT_ADDR0_A,
/openbmc/qemu/target/i386/kvm/
H A Dkvm.c4151 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, in kvm_put_msrs()
4576 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0); in kvm_get_msrs()
4928 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: in kvm_get_msrs()
4929 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data; in kvm_get_msrs()
/openbmc/qemu/target/i386/
H A Dcpu.h502 #define MSR_IA32_RTIT_ADDR0_A 0x580 macro
/openbmc/linux/arch/x86/kvm/
H A Dx86.c1460 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
7171 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: in kvm_probe_msr_to_save()
7173 (msr_index - MSR_IA32_RTIT_ADDR0_A >= in kvm_probe_msr_to_save()