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Searched refs:MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/x86/include/asm/
H A Dmsr-index.h456 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) macro
/openbmc/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h899 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) macro
/openbmc/linux/arch/x86/include/asm/
H A Dmsr-index.h921 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) macro