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Searched refs:MSR_IA32_L3_CBM_BASE (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/x86/kernel/cpu/resctrl/
H A Dcore.c74 .msr_base = MSR_IA32_L3_CBM_BASE,
141 if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) in cache_alloc_hsw_probe()
144 rdmsr(MSR_IA32_L3_CBM_BASE, l, h); in cache_alloc_hsw_probe()
/openbmc/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h1102 #define MSR_IA32_L3_CBM_BASE 0xc90 macro
/openbmc/linux/arch/x86/include/asm/
H A Dmsr-index.h1124 #define MSR_IA32_L3_CBM_BASE 0xc90 macro